Hitachi H8S/2199 Hardware Manual page 862

Single-chip microcomputer

Table of Contents

Bit 2    OSD Display Update Timing Control Bit (DTMV): Selects the timing for transfer of

data from master RAM to slave RAM and for OSD display update by register overwriting.

After the LDREQ bit is written to 1, data is transferred from master RAM to slave

RAM regardless of the Vsync signal (OSDV). The OSD display is updated

simultaneously with register* rewriting.

Note: * When transferring data using this setting, do not have the OSD display data

After the LDREQ bit is written to 1, data is transferred from master RAM to slave

RAM synchronously with the Vsync signal (OSDV). After rewriting the register, the

OSD display is updated synchronously with the Vsync signal (OSDV).

Note: The registers and register bits whose settings are reflected in the OSD display are the row

registers (CLINE), vertical display position register (VPOS), horizontal display position

DOBC bits of the digital output specification register (DOUT).

Bit 1    Master-Slave RAM Transfer Request and State Bit (LDREQ): Requests transfer of

data from master RAM to slave RAM. After this bit is written to 1, a transfer request is issued

with timing selected by the DTMV bit. When read, this bit indicates the state of data transfer from

master RAM to slave RAM.

Note: To abort data transfer after writing this bit to 1, write it to 0. However, once data transfer

begins it cannot be aborted.

Requests abort of data transfer from master RAM to slave RAM

Requests transfer of data from master RAM to slave RAM. After transfer is

completed, this bit is cleared to 0

Data is not being transferred from master RAM to slave RAM

Data is being transferred from master RAM to slave RAM, or is being prepared for

transfer. After transfer is completed, this bit is cleared to 0

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(Initial value)