Hitachi H8S/2199 Hardware Manual page 600

Single-chip microcomputer

Table of Contents

Bit 3    FIFO2 Overwrite Flag (OVWB): If a write is attempted when the FIFO2 is full of the

timing pattern data and the output pattern data (FLB bit = 1), the write operation becomes invalid,

an interrupt is generated, the OVWB flag is set to 1, and the write data is lost. Wait until space

becomes available in the FIFO2, then write again.

Write 0 to clear the OVWB flag, because it is not cleared automatically.

Normal operation.

Indicates that a write in FIFO2 was attempted when FIFO2 was full of data. Clear

this flag by writing 0 to this bit.

Bit 2    FIFO1 Overwrite Flag (OVWA): If a write is attempted when the FIFO1 is full of the

timing pattern data and the output pattern data (FLA bit = 1), the write operation becomes invalid,

an interrupt is generated, the OVWA flag is set to 1, and the write data is lost. Wait until space

becomes available in the FIFO1, then write again.

Write 0 to clear the OVWA flag, because it is not cleared automatically.

Normal operation.

Indicates that a write in FIFO1 was attempted when FIFO1 was full. Clear this

flag by writing 0 to this bit.

Bit 1    FIFO2 Pointer Clear (CLRB): Clears the FIFO2 write position pointer. After 1 is

written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.

Normal operation.

Clears the FIFO2 pointer.

Bit 0    FIFO1 Pointer Clear (CLRA): Clears the FIFO1 write position pointer. After 1 is

written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.

Normal operation

Clears the FIFO1 pointer

Rev. 1.0, 02/00, page 594 of 1141

(Initial value)