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Programming pulse apply subroutine
Enable WDT
Set PSU1 (2) bit in FLMCR1 (2)
Wait 50 µs
Set P1 (2) bit in FLMCR1 (2)
Wait for 10 µs, 30 µs or 200 µs
Clear P1(2) bit in FLMCR1 (2)
Wait 5 µs
Clear PSU1(2) bit in FLMCR1 (2)
Wait 5 µs
Disable WDT
End of subroutine
Note: 6. Programming pulse width
Number of times
Programming
of programming
time (z) µsec
1
30
2
30
3
30
4
30
5
30
6
30
7
200
8
200
9
200
10
200
11
200
12
200
13
200
998
200
999
200
1000
200
The programming pulse must be 10 µs in
additional programming
RAM
Program data storage are
(128 bytes)
Reprogram data storage
area (128 bytes)
Additional program data
storage area (128 bytes)
Perform programming after erasing data. Do not perform additional programming to addresses that have already been written to.
Notes: 1. Data transfer is performed by byte transfer. The lower eight bits of the start address must be H'00 or H'80. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes: in this case, H'FF must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even in case of the bit which is already-programmed in the 128-byte programming loop, perform additional programming if the bit fails at the next verify.
4. An area for storing program data (128 bytes), reprogram data (128 bytes), and additional program (128bytes) must be provided in RAM. The contents of the reprogram
and additional program areas are rewritten as programming processes.
5. A 30 µs or 200 µs programming pulse must be applied.
For details on programming pulse, refer to Notes*6.
To perform additional data programming, apply a programming pulse of 10 µs. Reprogram data X' is the reprogram data after program pulse is applied.
Reprogram Data Calculation Table
Source Data (D)
Verify data (V)
Reprogram data (X)
0
0
0
1
1
0
1
1
*5
Increment address
Transfer additional program data to additional program data area
Comments
1
Programming completed
0
Programming incomplete; reprogram
1
1
Still in erased state; no action
Figure 7.12 Program/Program-Verify Flowchart
Start
Set SWE1 (2) bit in FLMCR(2)
Wait 1 µs
Store 128-byte program data in program
data area and reprogram data area
n= 1
m= 0
Write 128-byte program data in RAM reprogram
data area consecutevely to flash memory
Call subroutine
Programming pulse 30 µs or 200 µs
Set PV1(2) bit in FLMCR1(2)
Wait 4 µs
H'FF dummy write to verify address
Wait 2 µs
Read verify data
Program data= verify data?
OK
NG
6 n?
OK
Calculate additional program data
Calculate reprogram data
Transfer reprogram data to reprogram data area
Complete 128-byte
data verification?
NG
OK
Clear PV1(2) bit in FLMCR1(2)
Wait 2 µs
NG
6 n ?
OK
Write 128-byte program data in RAM additional
data area consecutively to flash memory
Write pulse additional program pulse 10 µs
NG
m= 0?
OK
Clear SWE1(2) bit in FLMCR1(2)
Wait 100 µs
End of programming
Additiona l program data calculation table
Reprogram data (X')
Verify data (V)
0
0
0
1
1
0
1
1
*4
*1
Refer to note *6
for the pulse width
*2
NG
m= 1
*4
*3
*4
*1
n 1000?
OK
Clear SWE1 (2) bit in FLMCR1(2)
Wait 100 µs
Programming Failure
Additional program data (Y)
0
Additional programming performed
1
Additional programming not performed
1
1
Additional programming not performed
Rev. 1.0, 02/00, page 149 of 1141
n←n+1
NG
Comments
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