Page 1 Hitachi Single-Chip Microcomputer H8S/2215 Series Hardware Manual ADE-602-217B Rev. 3.0 10/04/02 Hitachi Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 4 Rev. 3.0, 10/02, page iv of lviii...
Page 5 Configuration of this Manual This manual comprises the following items: 1. Precautions in Relation to this Product 2. Configuration of this Manual 3. Overview 4. Table of Contents 5. Summary 6. Description of Functional Modules • CPU and System-Control Modules •...
Page 6 Rev. 3.0, 10/02, page vi of lviii...
Page 7 Note: * F-ZTAT is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2215 Series in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 8 H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor ADE-702-247 User’s Manual H8S, H8/300 Series Simulator Debugger (for Windows) Users Manual ADE-702-085 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging ADE-702-231 Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-201 Rev. 3.0, 10/02, page viii of lviii...
Page 9 List of Items Revised or Added for This Version Page Section Description 1.1 Overview Product Code Remarks • On-chip memory F-ZTAT Version HD64F2215 256 kbytes 16 kbytes SCI boot version HD64F2215U 256 kbytes 16 kbytes USB boot version Masked ROM HD6432215A 256 kbytes 16 kbytes...
Page 10 Page Section Description 1.3 Pin Arrangement Figure replaced Figure 1.3 Pin Arrangement (BP-112) P74/ PG1/ (Reserve) PE6/D6 PE3/D3 PE0/D0 PG4/ P71/ P34/RxD1 (Reserve) P72/ PD1/D9 PD0/D8 PE5/D5 PE2/D2 PG2/ P33/TxD1 P31/RxD0 TMO0/ P73/ P32/ PD4/D12 PD3/D11 PE7/D7 PE4/D4 PG3/ P30/TxD0 PF1/ TMO1/ SCK0/...
Page 11 Page Section Description Figure amended 7.1 Features Internal interrupts Figure 7.1 Block Diagram TGI0A of DMAC TGI1A TGI2A TXI0 RXI0 TXI1 RXI1 Control logic Note added 7.4.9 DMAC Bus Cycles 182, (Dual Address Mode) Note: * TEND output cannot be used with this LSI. Address amended 9.1.4 Pin Functions (Incorrect) Other than (B’1111)
Page 12 Page Section Description Figure amended 13.3.9 Serial Extended Mode Register 0 (SEMR_0) Figure 13.3 Examples of Base Clock when Average Transfer Rate is Selected Rev. 3.0, 10/02, page xii of lviii...
Page 13 Page Section Description Newly added Figure 13.4 Example of Average Transfer Rate Setting with TPU Clock Input Rev. 3.0, 10/02, page xiii of lviii...
Page 14 Page Section Description Added 13.7 SCI Select Function Note: * The selection signals (SEL_A and SEL_B) of the LSI Figure 13.24 Example of must be switched while the serial clock (M_SCK) is high after Communication Using the the end bit of the transmit data has been send. Note that one SCI Select Function selection signal can be brought low at the same time.
Page 15 Page Section Description Endpoint configuration based on Bluetooth standard 1.0 can 15.1 Features be specified. • Maximum Deleted Configuration, InterfaceNumber, and Newly added AlternateSetting • Maximum Configuration, InterfaceNumber, and configuration AlternateSetting configuration specifications of this LSI specifications of this Configuration 1 ----- InterfaceNumber 0 to 2 ----- LSI Configuration AlternateSetting 0 to 7 ----- EP0, EP1 to EP8 Figure 15.1 Block...
Page 16 Page Section Description Replaced 15.3.1 USB Endpoint Information Registers 00_0 UEPIRnn_1 to 22_4 (UEPIR00_0 to Bit Name Initial Value Description UEPIR22_4) 7 to D31 –D29 — Alternate number to which endpoint belongs (3-bit • UEPIRnn_1 configuration, settable values: 0 to 7) 000: Control transfer 001 to 111: Other than Control transfer —...
Page 17 Page Section Description 2nd line changed as follows 15.3.11 USB Endpoint Data Register 0s (Incorrect) Endpoint0 (UEDR0s) (Correct) Endpoint0s 9th line changed as follows 15.3.12 USB Endpoint Data Register 0i (UEDR0i) (Incorrect) Endpoint0 (Correct) Endpoint0i 15th line changed as follows 15.3.13 USB Endpoint Data Register 0o (Incorrect) Endpoint0...
Page 18 Page Section Description 2nd line changed as follows 15.3.23 USB Endpoint Receive Data Size (Incorrect) Endpoint2 Register 2o (UESZ2o) (Correct) Endpoint2o 4th line changed as follows (Incorrect) The FIFO for endpoint 2 out transfer has a dual- FIFO configuration (Correct) The FIFO for endpoint 2o (for Bulk_out transfer) has a dual-FIFO configuration line changed as follows 15.3.24 USB Endpoint...
Page 19 Page Section Description Bit table amended and Note added 15.3.42 USB Test Register 1 (UTSTR1) Bit Name Initial Value R/W Description VBUS —* Internal/External Transceiver Input Signal Monitor Bits —* VBUS: Monitors VBUS pin UBPM UBPM: Monitors UBPM pin 5 to 3 — Reserved These bits are always read as 0 and cannot be modified.
Page 20 Page Section Description Figure amended 15.5.9 Isochronous–Out Transfer (Dual-FIFO) USB function (When EP3o is Specified as Endpoint) Receive SOF Figure 15.21 EP3o Isochronous-Out Transfer Operation Switch to FIFO B-side UIFR1/EP3oTS, EP3oTF update FIFO A Receive OUT token Receive data from the host Receive data error? Set EP3o normal...
Page 21 Page Section Description Note *3 amended 15.8 USB External Circuit 521 to Example In HD64F2215, HD6432215A, HD6432215B, and HD6432215C, Pxx should be assigned to an output port as the D+ pull-up control pin. Figure 15.27 USB In HD64F2215U, in which on-chip ROM can be programmed by using the USB, P36 External Circuit in Bus- should be used as the D+ pull-up control pin.
Page 22 Page Section Description Explanation amended to 2nd line changed as follows 15.9.8 Reset A manual reset should not be performed during USB communication as the LSI will stop with the USD+USD- pin state maintained.This USB module uses synchronous reset for some registers. The reset state of these registers must be cancelled after the clock oscillation stabilization time has passed.
Page 23 Table newly added 19.1 Features • Size Product Category ROM Size ROM Addresses H'000000 to H'03FFFF H8S/2215 Series HD64F2215,HD64F2215U 256 kbytes (Modes 6 and 7) Description added • Two flash memory  Boot mode (SCI boot mode: HD64F2215, USB boot...
Page 24 (Incorrect) Boot Mode (Correct) SCI Boot Mode Figure 19.6 SCI System Figure amended Configuration in Boot Mode H8S/2215 Series FWE* MD2 to 0* Flash memory Note added to figure Note: * FWE pin and mode pin input must satisfy the mode...
Page 25 Page Section Description Bit name amended 21.1.2 Low-Power Control Register Bit Name Initial Value R/W Description (LPWRCR) 7 to — These bits can be read from or written to, but the write value should always be 0. RFCUT Built-in Feedback Resistor Control: Selects whether the oscillator’s built-in feedback resistor and duty adjustment circuit are used with external clock input.
Page 26 Page Section Description 24.3 DC Characteristics Table amended Test Table 24.2 DC Item Symbol Unit Conditions Characteristics × – Schmitt IRQ0 to IRQ5 V — — trigger input ⋅ 0.8 — — IRQ7 voltage × 0.05 – – V — —...
Page 27 Unit: mm 10.00 0.20 C A 11 10 9 4 × 0.15 0.80 1.00 112 × φ0.50 ± 0.05 φ0.08 0.10 Hitachi Code BP-112 JEDEC – JEITA – Mass (reference value) 0.3 g Rev. 3.0, 10/02, page xxvii of lviii...
Page 28 Rev. 3.0, 10/02, page xxviii of lviii...
Page 29: Table Of Contents
Contents Section 1 Overview....................1 Overview........................... 1 Internal Block Diagram..................... 2 Pin Arrangement ....................... 3 Pin Functions in Each Operating Mode ................5 Pin Functions ........................10 Section 2 CPU....................19 Features..........................19 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........20 2.1.2 Differences from H8/300 CPU ................
Page 30 Usage Notes........................53 2.9.1 Note on TAS Instruction Usage ................53 2.9.2 STM/LTM Instruction Usage................53 2.9.3 Note on Bit Manipulation Instructions ..............54 Section 3 MCU Operating Modes..............55 Operating Mode Selection....................55 Register Descriptions ......................56 3.2.1 Mode Control Register (MDCR)................56 3.2.2 System Control Register (SYSCR) ..............57 Operating Mode Descriptions....................58 3.3.1 Mode 4 .........................58...
Page 31 5.4.2 Internal Interrupts ....................84 Interrupt Exception Handling Vector Table..............84 Interrupt Control Modes and Interrupt Operation ............. 87 5.6.1 Interrupt Control Mode 0 ..................87 5.6.2 Interrupt Control Mode 2 ..................89 5.6.3 Interrupt Exception Handling Sequence .............. 91 5.6.4 Interrupt Response Times ..................
Page 32 6.10 Bus Arbitration ........................138 6.10.1 Operation......................138 6.10.2 Bus Transfer Timing ....................138 6.10.3 External Bus Release Usage Note ................139 6.11 Resets and the Bus Controller ...................139 Section 7 DMA Controller.................141 Features ..........................141 Register Configuration ......................143 Register Descriptions ......................145 7.3.1 Memory Address Registers (MAR)..............145 7.3.2 I/O Address Register (IOAR)................145 7.3.3...
Page 33 Register Descriptions ......................197 8.2.1 DTC Mode Register A (MRA) ................197 8.2.2 DTC Mode Register B (MRB)................198 8.2.3 DTC Source Address Register (SAR)..............198 8.2.4 DTC Destination Address Register (DAR)............198 8.2.5 DTC Transfer Count Register A (CRA) .............. 198 8.2.6 DTC Transfer Count Register B (CRB)...............
Page 34 Port 4 ..........................228 9.3.1 Port 4 Register (PORT4) ..................228 9.3.2 Pin Function ......................228 Port 7 ..........................229 9.4.1 Port 7 Data Direction Register (P7DDR) .............229 9.4.2 Port 7 Data Register (P7DR) ................229 9.4.3 Port 7 Register (PORT7) ..................230 9.4.4 Pin Functions......................230 Port 9 ..........................232 9.5.1 Port 9 Register (PORT9) ..................232...
Page 35 9.10.3 Port E Register (PORTE)..................252 9.10.4 Port E Pull-up MOS Control Register (PEPCR)..........252 9.10.5 Pin Functions ....................... 253 9.10.6 Port E Input Pull-Up MOS State................254 9.11 Port F..........................255 9.11.1 Port F Data Direction Register (PFDDR) ............256 9.11.2 Port F Data Register (PFDR) ................
Page 36 10.7.1 Input/Output Timing ....................313 10.7.2 Interrupt Signal Timing..................316 10.8 Usage Notes........................320 Section 11 8-Bit Timers (TMR).................327 11.1 Features ..........................327 11.2 Input/Output Pins ......................329 11.3 Register Descriptions ......................329 11.3.1 Timer Counters (TCNT)..................329 11.3.2 Time Constant Registers A (TCORA) ..............329 11.3.3 Time Constant Registers B (TCORB) ..............329 11.3.4 Time Control Registers (TCR) ................329 11.3.5 Timer Control/Status Registers (TCSR)...............332 11.4 Operation...........................334...
Page 37 12.3.1 Watchdog Timer Mode ..................351 12.3.2 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......352 12.3.3 Interval Timer Mode.................... 353 12.3.4 Timing of Setting of Overflow Flag (OVF)............353 12.4 Interrupts........................... 354 12.5 Usage Notes ........................354 12.5.1 Notes on Register Access..................
Page 38 (Clocked Synchronous Mode)................403 13.7 SCI Select Function......................405 13.8 Interrupts ...........................408 13.8.1 Interrupts in Normal Serial Communication Interface Mode.......408 13.9 Usage Notes........................409 13.9.1 Break Detection and Processing (Asynchronous Mode Only) ......409 13.9.2 Mark State and Break Detection (Asynchronous Mode Only)......409 13.9.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..............410 13.9.4 Restrictions on Use of DMAC or DTC ..............410 13.9.5 Operation in Case of Mode Transition ..............410...
Page 39 15.3.14 USB Endpoint Data Register 1i (UEDR1i)............458 15.3.15 USB Endpoint Data Register 2i (UEDR2i)............458 15.3.16 USB Endpoint Data Register 2o (UEDR2o)............458 15.3.17 USB Endpoint Data Register 3i (UEDR3i)............459 15.3.18 USB Endpoint Data Register 3o (UEDR3o)............459 15.3.19 USB Endpoint Data Register 4i (UEDR4i)............
Page 40 15.5.11 Stall Operations ....................508 15.6 DMA Transfer Specifications....................513 15.6.1 Overview ......................513 15.6.2 On-Chip DMAC Settings ..................513 15.6.3 EP2i and EP4i DMA Transfer................513 15.6.4 EP2o and EP4o DMA Transfer ................513 15.6.5 EP2iPKTE, EP4iPKTE, EP2oRDFN and EP4oRDFN Bits of UTRG....514 15.7 Endpoint Configuration Example..................516 15.8 USB External Circuit Example ..................521 15.9 Usage Notes........................525 15.9.1 Operating Frequency ....................525...
Page 41 16.8.4 Notes on Board Design ..................548 16.8.5 Notes on Noise Countermeasures ................ 548 Section 17 D/A Converter..................551 17.1 Features..........................551 17.2 Input/Output Pins ......................552 17.3 Register Description......................552 17.3.1 D/A Data Register (DADR)................552 17.3.2 D/A Control Register (DACR) ................553 17.4 Operation ..........................
Page 42 Section 20 Masked ROM...................593 20.1 Features ..........................593 Section 21 Clock Pulse Generator ..............595 21.1 Register Descriptions ......................596 21.1.1 System Clock Control Register (SCKCR)............596 21.1.2 Low-Power Control Register (LPWRCR)............598 21.2 System Clock Oscillator ....................599 21.2.1 Connecting a Crystal Resonator ................599 21.2.2 Inputting an External Clock .................600 21.3 Duty Adjustment Circuit ....................601 21.4 Medium-Speed Clock Divider...................601 21.5 Bus Master Clock Selection Circuit ..................601...
Page 43 22.6 Module Stop Mode ......................620 22.7 ø Clock Output Disabling Function .................. 620 22.8 Usage Notes ........................621 22.8.1 I/O Port Status...................... 621 22.8.2 Current Dissipation during Oscillation Stabilization Wait Period ....... 621 22.8.3 DMAC and DTC Module Stop ................621 22.8.4 On-Chip Supporting Module Interrupt ..............
Page 44 Figures Section 1 Overview Figure 1.1 Internal Block Diagram ....................2 Figure 1.2 Pin Arrangement (TFP-120) ..................3 Figure 1.3 Pin Arrangement (BP-112)..................4 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ..............23 Figure 2.2 Stack Structure in Normal Mode ................23 Figure 2.3 Exception Vector Table (Advanced Mode) ...............
Page 45 Section 6 Bus Controller Figure 6.1 Block Diagram of Bus Controller................100 Figure 6.2 Overview of Area Divisions..................110 CSn Signal Output Timing (n = 0 to 7) ..............113 Figure 6.3 Figure 6.4 On-Chip Memory Access Cycle................114 Figure 6.5 Pin States during On-Chip Memory Access............
Page 46 Figure 7.16 Example of Short Address Mode Transfer .............. 182 Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer........... 183 Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer .......... 183 Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer......184 Figure 7.20 Example of DREQ Level Activated Normal Mode Transfer ........
Page 47 Figure 10.14 Example of Synchronous Operation Setting Procedure......... 298 Figure 10.15 Example of Synchronous Operation..............299 Figure 10.16 Compare Match Buffer Operation ................. 299 Figure 10.17 Input Capture Buffer Operation................300 Figure 10.18 Example of Buffer Operation Setting Procedure........... 300 Figure 10.19 Example of Buffer Operation (1)................
Page 48 Figure 11.2 Example of Pulse Output ..................334 Figure 11.3 Count Timing for Internal Clock Input..............335 Figure 11.4 Count Timing for External Clock Input..............335 Figure 11.5 Timing of CMF Setting ................... 336 Figure 11.6 Timing of Timer Output ..................336 Figure 11.7 Timing of Compare Match Clear................
Page 49 Figure 13.15 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)......394 Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (1) ........395 Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (2) ........396 Figure 13.17 Data Format in Synchronous Communication (For LSB-First)......397 Figure 13.18 Sample SCI Initialization Flowchart ..............
Page 50 Figure 15.12 Setup Stage Operation ................... 493 Figure 15.13 Data Stage Operation (Control-In)................. 495 Figure 15.14 Data Stage Operation (Control-Out) ..............496 Figure 15.15 Status Stage Operation (Control-In) ..............497 Figure 15.16 Status Stage Operation (Control-Out)..............498 Figure 15.17 EP1i Interrupt-In Transfer Operation..............499 Figure 15.18 EP2i Bulk-In Transfer Operation................
Page 51 Section 19 Flash Memory (F-ZTAT Version) Figure 19.1 Block Diagram of Flash Memory................558 Figure 19.2 Flash Memory State Transitions................559 Figure 19.3 Boot Mode....................... 561 Figure 19.4 User Program Mode ....................562 Figure 19.5 Flash Memory Block Configuration................ 563 Figure 19.6 SCI System Configuration in Boot Mode ...............
Page 52 Figure 24.4 Oscillation Stabilization Timing................656 Figure 24.5 Reset Input Timing ....................657 Figure 24.6 Interrupt Input Timing ..................... 657 Figure 24.7 Basic Bus Timing (Two-State Access) ..............659 Figure 24.8 Basic Bus Timing (Three-State Access) ..............660 Figure 24.9 Basic Bus Timing (Three-State Access with One Wait State)......... 661 Figure 24.10 Burst ROM Access Timing (Two-State Access) ...........
Page 53 Tables Section 2 CPU Table 2.1 Instruction Classification .................... 35 Table 2.2 Operation Notation...................... 36 Table 2.3 Data Transfer Instructions................... 37 Table 2.4 Arithmetic Operations Instructions (1) ............... 38 Table 2.4 Arithmetic Operations Instructions (2) ............... 39 Table 2.5 Logic Operations Instructions ..................40 Table 2.6 Shift Instructions ......................
Page 54 Table 6.5 Pin States in Bus Released State ................136 Section 7 DMA Controller Table7.1 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0)..............143 Table 7.2 DMAC Transfer Modes..................... 163 Table 7.3 Register Functions in Sequential Mode..............164 Table 7.4 Register Functions in Idle Mode ................
Page 55 Table 9.16 P30 Pin Function....................... 228 Table 9.17 P74 Pin Function....................... 230 Table 9.18 P73 Pin Function....................... 230 Table 9.19 P72 Pin Function....................... 231 Table 9.20 P71 Pin Function....................... 231 Table 9.21 P70 Pin Function....................... 231 Table 9.22 PA3 Pin Function ...................... 235 Table 9.23 PA2 Pin Function ......................
Page 56 Table 9.59 PE2 Pin Function....................... 254 Table 9.60 PE1 Pin Function....................... 254 Table 9.61 PE0 Pin Function....................... 254 Table 9.62 Input Pull-Up MOS States (Port E) ................255 Table 9.63 PF7 Pin Function....................... 257 Table 9.64 PF6 Pin Function....................... 257 Table 9.65 PF5 Pin Function.......................
Page 57 Section 11 8-Bit Timers (TMR) Table 11.1 Pin Configuration...................... 329 Table 11.2 Clock Input to TCNT and Count Condition.............. 332 Table 11.3 8-Bit Timer Interrupt Sources ................... 340 Table 11.4 Timer Output Priorities ..................... 344 Table 11.5 Switching of Internal Clock and TCNT Operation ........... 345 Section 12 Watchdog Timer Table 12.1 WDT Interrupt Source ....................
Page 58 Table 16.5 A/D Converter Interrupt Source ................544 Table 16.6 Analog Pin Specifications ..................549 Section 17 D/A Converter Table 17.1 Pin Configuration ...................... 552 Section 19 Flash Memory (F-ZTAT Version) Table 19.1 Differences between Boot Mode and User Program Mode........560 Table 19.2 Pin Configuration ......................
Page 59: Section 1 Overview
Section 1 Overview Overview • High-speed H8S/2000 central processing unit with 16-bit architecture  Upward-compatible with H8/300 and H8/300H CPUs on an object level  Sixteen 16-bit general registers  65 basic instructions • Various peripheral functions  DMA controller (DMAC) ...
Page 60: Internal Block Diagram
Internal Block Diagram Port D Port E Boundary scan PA3/A19/SCK2/SUSPND PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 EXTAL PB7/A15 XTAL PB6/A14 PLLVCC PLL for H8S/2000 CPU PB5/A13 PLLCAP PB4/A12 PLLVSS PB3 / A11 EXTAL48 PB2/A10 XTAL48 PB1/A9 PB0/A8 DMAC Interrupts controller PC7/A7 FWE* PC6/A6 USPND PC5/A5 USD+...
Page 61: Pin Arrangement
Pin Arrangement P33/TxD1 DrVSS P34/RxD1 USD- P35/SCK1/ USD+ DrVCC RESERVE P74/ VBUS P73/TMO1/ RESERVE P72/TMO0/ USPND P71/ RESERVE P70/TMRI01/TMCI01/ AVCC Vref PG1/ P40/AN0 PG2/ P41/AN1 PG3/ P42/AN2 PG4/ P43/AN3 TFP-120 P96/AN14/DA0 (Pin Arrangement) P97/AN15/DA1 AVSS P17/TIOCB2/TCLKD/ P16/TIOCA2/ PE0/D0 P15/TIOCB1/TCLKC/FSE0 RESERVE P14/TIOCA1/ PE1/D1 P13/TIOCD0/TCLKB/A23/VPO...
Page 62: Figure 1.3 Pin Arrangement (Bp-112)
P74/ PG1/ (Reserve) PE6/D6 PE3/D3 PE0/D0 PG4/ P71/ P34/RxD1 (Reserve) P72/ PD1/D9 PD0/D8 PE5/D5 PE2/D2 PG2/ P33/TxD1 P31/RxD0 TMO0/ P73/ P32/ PD4/D12 PD3/D11 PE7/D7 PE4/D4 PG3/ P30/TxD0 PF1/ TMO1/ SCK0/ P70/ P35/ PF0/ TMRI01/ PD7/D15 PD6/D14 PD5/D13 PD2/D10 PE1/D1 SCK1/ PF2/ PF4/ TMCI01/...
Page 63: Pin Functions In Each Operating Mode
Pin Functions in Each Operating Mode Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7* PROM Mode — Reserved Reserved Reserved Reserved PC1/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB0/A8 PB0/A8 PB1/A9 PB1/A9 PB1/A9 —...
Page 64 Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7* PROM Mode PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2 PA3/A19/SCK2/ PA3/A19/SCK2/ PA3/A19/SCK2/ PA3 /SCK2 SUSPND SUSPND SUSPND — RESERVE RESERVE RESERVE RESERVE P10/TIOCA0/ P10/TIOCA0/ P10/TIOCA0/ P10/TIOCA0 A20/VM A20/VM A20/VM P11/TIOCB0/ P11/TIOCB0/ P11/TIOCB0/...
Page 65 Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7* PROM Mode DrVCC DrVCC DrVCC USD+ USD+ USD+ — USD- USD- USD- — DrVSS DrVSS DrVSS — — PLLVSS PLLVSS PLLVSS — PLLCAP PLLCAP PLLCAP PLLVCC PLLVCC PLLVCC —...
Page 66 Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7* PROM Mode P30/TxD0 P30/TxD0 P30/TxD0 P30/TxD0 P31/RxD0 P31/RxD0 P31/RxD0 P31/RxD0 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4 P32/SCK0/IRQ4 NC P33/TxD1 P33/TxD1 P33/TxD1 P33/TxD1 P34/RxD1 P34/RxD1 P34/RxD1 P34/RxD1 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5 P35/SCK1/IRQ5 NC —...
Page 67 Pin No. Pin Name TFP-120 BP-112 Mode 4 Mode 5 Mode 6 Mode 7* PROM Mode PE6/D6 PE6/D6 PE6/D6 PE7/D7 PE7/D7 PE7/D7 — A1, A11, RESERVE RESERVE RESERVE RESERVE L1, L11 Note : * The USB cannot be used in mode 7. Rev.
Page 68: Pin Functions
Pin Functions Pin No. Type Symbol TFP-120 BP-112 Function Power Supply Input Power supply pins. Connect all these pins to the system power supply. Input Ground pins. Connect all these pins to the system power supply (0 V). PLLVCC Input Power supply pin for internal PLL oscillator.
Page 69 Pin No. Type Symbol TFP-120 BP-112 Function System Input Reset input pin. When this pin is Control driven low, the chip is reset. STBY Input When this pin is driven low, a transition is made to hardware standby mode. MRES Input When this pin is driven low, a transition is made to manual reset...
Page 70 Pin No. Type Symbol TFP-120 BP-112 Function Address bus Output These pins output an address. Rev. 3.0, 10/02, page 12 of 686...
Page 71 Pin No. Type Symbol TFP-120 BP-112 Function Data bus These pins constitute a bi-directional data bus. Bus Control Output Signals for selecting areas 7 to 0. Output When this pin is low, it indicates that address output on the address bus is enabled.
Page 72 Pin No. Type Symbol TFP-120 BP-112 Function 16-bit timer TCLKA Input TPU external clock input pins. pulse unit TCLKB (TPU) TCLKC TCLKD TIOCA0 The TGRA_0 to TGRD_0 input capture input/output compare TIOCB0 output/PWM output pins. TIOCC0 TIOCD0 TIOCA1 The TGRA_1 to TGRB_1 input capture input/output compare TIOCB1 output/PWM output pins.
Page 73 Pin No. Type Symbol TFP-120 BP-112 Function D/A converter DA1 Output Analog output pins for the D/A converter. A/D converter AVCC Input Power supply pin for the A/D and D/A converter. When the D/A converter is D/A converter not used, connect this pin to the system power supply(VCC).
Page 74 Pin No. Type Symbol TFP-120 BP-112 Function UBPM Input Bus power/self power mode setting Input. When the USB is used in bus power mode, this input pin must be fixed low. When the USB is used in self power mode, this input pin must be fixed high.
Page 75 Pin No. Type Symbol TFP-120 BP-112 Function I/O port Input 2-bit input pins 4-bit I/O pins 8-bit I/O pins 8-bit I/O pins 8-bit I/O pins 8-bit I/O pins Rev. 3.0, 10/02, page 17 of 686...
Page 76 Pin No. Type Symbol TFP-120 BP-112 Function I/O port 8-bit I/O pins 8-bit I/O pins 5-bit I/O pins  Reserve RESERVE 1 Reserved pins These pins should be open and should not be connected to any device. Rev. 3.0, 10/02, page 18 of 686...
Page 77: Section 2 Cpu
Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU.
Page 78: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
• Two CPU operating modes  Normal mode*  Advanced mode Note : * Normal mode is not available in this LSI. • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Page 79: Differences From H8/300 Cpu
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added.
Page 80: Cpu Operating Modes
CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU.
Page 81: Advanced Mode
H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 Exception H'0007 vector table H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode) EXR* (16 bits) Reserved* SP *...
Page 82: Figure 2.3 Exception Vector Table (Advanced Mode)
• Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3).
Page 83: Figure 2.4 Stack Structure In Advanced Mode
EXR* Reserved Reserved* (24 bits) (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: *1 When EXR is not used, it is not stored on the stack. SP when EXR is not used. Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode Rev.
Page 84: Address Space
Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 85: Register Configuration
Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers (CR)
Page 86: General Registers
2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 87: Program Counter (Pc)
Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
Page 88: Condition-Code Register (Ccr)
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 89 Bit Name Initial Value R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence.
Page 90: Initial Register Values
2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized.
Page 91: Figure 2.9 General Register Data Formats (2)
Data Type Register Number Data Image Word data Word data Longword data Legend : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 92: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 93: Instruction Set
Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L operations ADDX, SUBX, DAA, DAS...
Page 94: Table Of Instructions Classified By Function
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarizes the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source) * General register* General register (32-bit register) (EAd)
Page 95: Table 2.3 Data Transfer Instructions
Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI. MOVTPE Cannot be used in this LSI.
Page 96: Table 2.4 Arithmetic Operations Instructions (1)
Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
Page 97: Table 2.4 Arithmetic Operations Instructions (2)
Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 98: Table 2.5 Logic Operations Instructions
Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 99: Table 2.7 Bit Manipulation Instructions (1)
Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 100: Table 2.7 Bit Manipulation Instructions (2)
Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 101: Table 2.8 Branch Instructions
Table 2.8 Branch Instructions Instruction Size Function – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 102: Table 2.9 System Control Instruction
Table 2.9 System Control Instruction Instruction Size* Function TRAPA – Starts trap-instruction exception handling. – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory.
Page 103: Basic Instruction Formats
2.6.2 Basic Instruction Formats The H8S/2215 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats.
Page 104: Addressing Modes And Effective Address Calculation
(1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm, etc. EA(disp) (4) Operation field, effective address extension, and condition field EA(disp) BRA d:16, etc.
Page 105: Register Direct-Rn
2.7.1 Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers.
Page 106: Immediate-#Xx:8, #Xx:16, Or #Xx:32
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Normal Mode* Advanced Mode Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16)
Page 107: Effective Address Calculation
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be H'00. Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling.
Page 108: Table 2.13 Effective Address Calculation (1)
Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents. Register indirect (@ERn) General register contents General register contents Sign extension Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ General register contents...
Page 109: Table 2.13 Effective Address Calculation (2)
Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Note: * Normal mode is not available in this LSI. Rev.
Page 110: Processing States
Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State In this state the CPU and internal peripheral modules are all initialized and stop. When the RES input goes low all current processing stops and the CPU enters the reset state.
Page 111: Usage Notes
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.
Page 112: Note On Bit Manipulation Instructions
For four registers: ER0 to ER3 For the Hitachi H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction including ER7 is not created. 2.9.3 Note on Bit Manipulation Instructions Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte units, perform bit manipulation, and write data in byte units.
Page 113: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Operating Mode Selection This LSI supports four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0) as show in table 3.1. Do not change the mode pin settings during operation.
Page 114: Register Descriptions
Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode of this LSI. Bit Name Initial Value R/W Description –...
Page 115: System Control Register (Syscr)
3.2.2 System Control Register (SYSCR) SYSCR is used to select the interrupt control mode and the detected edge for NMI, select the MRES input pin enable or disable, and enables or disables on-chip RAM. Bit Name Initial Value R/W Description –...
Page 116: Operating Mode Descriptions
Operating Mode Descriptions This LSI has four operating modes, mode 4 to mode 7. Modes 4 to 6 are extended modes in which external memory and external peripheral devices can be accessed. In extended modes, each area can be used as 8-bit or 16-bit address space according to the bus controller settings after program execution.
Page 117: Mode 6
Port C always has an address (A7 to A0) output function. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus.
Page 118: Table 3.2 Pin Functions In Each Operating Mode
Table 3.2 Pin Functions in Each Operating Mode Port Mode 4 Mode 5 Mode 6 Mode 7* Port 1 P13 to P11 P*/A P*/A P*/A P/A* P/A* P*/A Port A PA3 to PA0 P/A* P/A* P*/A Port B P/A* P/A* P*/A Port C P*/A...
Page 119: Memory Map In Each Operating Mode
Memory Map in Each Operating Mode Figures 3.1 to 3.3 show the memory map in each operating mode for HD64F2215, HD64F2215U, HD6432215A, HD6432215B, and HD6432215C. Modes 4 and 5 Mode 6 Mode 7* (advanced extended modes (advanced extended mode (advanced single-chip mode) with on-chip ROM desabled) with on-chip ROM enabled) H'000000...
Page 120: Figure 3.2 Memory Map In Each Operating Mode For Hd6432215B
Modes 4 and 5 Mode 6 Mode 7* (advanced extended modes (advanced extended mode (advanced single-chip mode) with on-chip ROM desabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'01FFFF H'020000 Reserved External address H'040000 space External address space H'C00000 H'C00000...
Page 121: Figure 3.3 Memory Map In Each Operating Mode For Hd6432215C
Modes 4 and 5 Mode 6 Mode 7* (advanced extended modes (advanced extended mode (advanced single-chip mode) with on-chip ROM desabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'00FFFF H'010000 Reserved External address H'040000 space External address space H'C00000 H'C00000...
Page 122 Rev. 3.0, 10/02, page 64 of 686...
Page 123: Section 4 Exception Handling
Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 124: Table 4.2 Exception Handling Vector Table
Table 4.2 Exception Handling Vector Table Vector Address* Exception Source Vector Number Normal Mode* Advanced Mode Power-on reset H'0000 to H'0001 H'0000 to H'0003 Manual reset H'0002 to H'0003 H'0004 to H'0007 Reserved for system use H'0004 to H'0005 H'0008 to H'000B H'0006 to H'0007 H'000C to H'000F H'0008 to H'0019...
Page 125: Reset
Reset A reset has the highest exception priority. When the RES or MRES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES or MRES pin low for at least 20 ms at power-up or hold the RES or MRES pin low for at least 20 states during operation.
Page 126: Reset Exception Handling
4.3.2 Reset Exception Handling When the RES or MRES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
Page 127: Interrupts After Reset
Internal Prefetch of first Vector fetch processing program instruction Address bus High D15 to D0 (1) (3) Reset exception handling vector address (for power-on reset, (1) = H'000000, (3) = H'000002; for manual reset, (1) = H'000004, (3) = H'000006) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4))
Page 128: Traces
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
Page 129: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved in the stack.
Page 130: Stack Status After Exception Handling
Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes Reserved* CCR* CCR* PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes Reserved* PC (24 bits)
Page 131: Notes On Use Of The Stack
Notes on Use of the Stack When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP)
Page 132 Rev. 3.0, 10/02, page 74 of 686...
Page 133: Section 5 Interrupt Controller
Section 5 Interrupt Controller Features • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR  An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
Page 134: Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number ISCR Priority determination Internal interrupt request I2 to I0 SWDTEND to EXIRQ1 Interrupt controller Legend: : IRQ sense control register...
Page 135: Input/Output Pins
Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name Function Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ7 Input Maskable external interrupts; rising, falling, or both edges, or level sensing, (IRQ6 is an interrupt signal only for the on-chip USB) can be IRQ5 Input...
Page 136: Interrupt Priority Registers A To G, I To K, M (Ipra To Iprg, Ipri To Iprk, Iprm)
5.3.1 Interrupt Priority Registers A to G, I to K, M (IPRA to IPRG, IPRI to IPRK, IPRM) The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
Page 137: Irq Enable Register (Ier)
5.3.2 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Name Initial Value R/W Description IRQ7E IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. IRQ6E IRQ6 Enable* The IRQ6 interrupt request is enabled when this bit is 1. IRQ5E IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1.
Page 138: Irq Sense Control Registers H And L (Iscrh, Iscrl)
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7, and IRQ5 to IRQ0. Bit Name Initial Value R/W Description IRQ7SCB IRQ7 Sense Control B IRQ7SCA IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7...
Page 139 Bit Name Initial Value R/W Description IRQ3SCB IRQ3 Sense Control B IRQ3SCA IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input low level 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input...
Page 140: Irq Status Register (Isr)
5.3.4 IRQ Status Register (ISR) ISR indicates the status of IRQ7 to IRQ0 interrupt requests. Only 0 should be written to these bits for clearing the flag. Bit Name Initial Value R/W Description IRQ7F [Setting conditions] When the interrupt source selected by the ISCR IRQ6F registers occurs IRQ5F...
Page 141: Interrupt Sources
Interrupt Sources 5.4.1 External Interrupts There are eight external interrupts: NMI, IRQ7, and IRQ5 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. IRQ6 is an interrupt only for the on-chip USB. However, IRQ6 is functionally same as IRQ7 restore this LSI from software standby mode. IRQ6 is functionally same as IRQ7 and IRQ5 to IRQ0.
Page 142: Internal Interrupts
5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller.
Page 143: Table 5.2 Interrupt Sources, Vector Addresses, And Interrupt Priorities
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Interrupt Origin of Interrupt Vector Source Source Number Advanced Mode Priority External pins H'001C High IRQ0 H'0040 IPRA6–IPRA4 IRQ1 H'0044 IPRA2–IPRA0 IRQ2 H'0048 IPRB6–IPRB4 IRQ3 H'004C IRQ4 H'0050 IPRB2–IPRB0 IRQ5 H'0054 IRQ6...
Page 144 Interrupt Origin of Interrupt Vector Source Source Number Vector Address* Priority 8-bit timer CMIA1 (compare H'0110 IPRI2–IPRI0 High channel 1 match A) CMIB1 (compare H'0114 match B) OVI1 (overflow) H'0118 DMAC DEND0A H'0120 IPRJ6–IPRJ4 DEND0B H'0124 DEND1A H'0128 DEND1B H'012C SIC channel 0 ERI0 H'0140...
Page 145: Interrupt Control Modes And Interrupt Operation
Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
Page 146: Figure 5.3 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 0
Program execution status Interrupt generated? Hold I = 0 pending IRQ0 IRQ1 EXIRQ1 Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.0, 10/02, page 88 of 686...
Page 147: Interrupt Control Mode 2
5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
Page 148: Figure 5.4 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 2
Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Hold Save PC, CCR, and EXR pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in...
Page 149: Interrupt Exception Handling Sequence
5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.5 Interrupt Exception Handling Rev.
Page 150: Interrupt Response Times
5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times  the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Page 151: Dtc Activation By Interrupt
5.6.5 DTC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Activation request to DMAC • Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC and DMAC, see section 8, Data Transfer Controller (DTC) and section 7, DMA Controller.
Page 152 activation factor for that DMAC cannot act as the DTC activation factor or the CPU interrupt factor. Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation request or CPU interrupt request by the DTCERA to DTCERF of DTC and the DTCE bit of DTCERI.
Page 153: Usage Notes
Table 5.6 Interrupt Source Selection and Clearing Control Settings DMAC Interrupt Sources Selection/Clearing Control DTCE DISEL DMAC ∆ Ο ∆ Ο ∆ ∆ Ο Ο *: Don’t care Legend: Ο: The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) ∆: The relevant interrupt is used.
Page 154: Instructions That Disable Interrupts
TIER0 write cycle by CPU TGI0A exception handling φ Internal TIER_0 address address bus Internal write signal TGIEA TGFA TGI0A Interrupt signal Figure 5.7 Contention between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed.
Page 155 With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
Page 156 Rev. 3.0, 10/02, page 98 of 686...
Page 157: Section 6 Bus Controller
Section 6 Bus Controller This LSI has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). Features •...
Page 158: Figure 6.1 Block Diagram Of Bus Controller
Figure 6.1 shows a block diagram of the bus controller. Chip select signals Internal Area decorder address bus ABWCR External bus control signals ASTCR BCRH BCRL Internal control controller signals Bus mode signal Wait controller WCRH WCRL CPU bus request signal DTC bus request signal DMAC bus request signal Bus arbiter...
Page 159: Input/Output Pins
Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Pin Configuration Name Symbol Function Address strove Output Strobe signal indicating that address output on address bus is enabled. Read Output Strobe signal indicating that external space is being read.
Page 160: Access State Control Register (Astcr)
ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers except for the on-chip USB is fixed regardless of the settings in ABWCR. Bit Name Initial Value R/W Description ABW7 1/0* Area 7 to 0 Bus Width Controls:...
Page 161: Wait Control Registers H And L (Wcrh, Wcrl)
6.3.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers except for the on-chip USB. •...
Page 162 Bit Name Initial Value R/W Description Area 5 Wait Control 1 and 0: These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. 00: Program wait not inserted when external space area 5 is accessed 01: 1 program wait state inserted when external space...
Page 163 • WCRL Bit Name Initial Value R/W Description Area 3 Wait Control 1 and 0: These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. 00: Program wait not inserted when external space area 3 is accessed 01: 1 program wait state inserted when external space...
Page 164 Bit Name Initial Value R/W Description Area 0 Wait Control 1 and 0: These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. 00: Program wait not inserted when external space area 0 is accessed 01: 1 program wait state inserted when external space...
Page 165: Bus Control Register H (Bcrh)
6.3.4 Bus Control Register H (BCRH) BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. Bit Name Initial Value R/W Description ICIS1 Idle Cycle Insert 1: Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Page 166: Bus Control Register L (Bcrl)
6.3.5 Bus Control Register L (BCRL) BCRL performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. Bit Name Initial Value R/W Description BRLE Bus release enable: Enables or disables external bus release. 0: External bus release is disabled. BREQ and BACK can be used as I/O ports.
Page 167: Pin Function Control Register (Pfcr)
6.3.6 Pin Function Control Register (PFCR) PFCR performs address output control in external extended mode. Bit Name Initial Value R/W Description 7 to – Reserved The write value should always be 0. 1/0* Address Output Enable 3 to 0: 1/0* These bits select enabling or disabling of address outputs A8 to A23 in ROMless extended mode and modes with ROM.
Page 168: Bus Control
Bus Control 6.4.1 Area Divisions In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map.
Page 169: Bus Specifications
6.4.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers except for the on-chip USB are fixed, and are not affected by the bus controller.
Page 170: Bus Interface For Each Area
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWn ASTn Bus Width Number of Access Number of Program States Wait States     6.4.3 Bus Interface for Each Area The initial state of each area is basic bus interface, 3-state access space.
Page 171: Chip Select Signals
6.4.4 Chip Select Signals This LSI can output chip select signals (CS0 to CS7 ) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing.
Page 172: Basic Timing
Basic Timing The CPU is driven by a system clock (ø), denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state". The memory cycle or bus cycle consists of one, two, or three states.
Page 173: On-Chip Peripheral Module Access Timing
Bus cycle Address bus Unchanged High High High Data bus High-impedance state Figure 6.5 Pin States during On-Chip Memory Access 6.5.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states except on-chip USB. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed.
Page 174: External Address Space Access Timing
Bus cycle Address bus Unchanged High High High Data bus High-impedance state Figure 6.7 Pin States during On-Chip Peripheral Module Access 6.5.3 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle.
Page 175: Basic Bus Interface
Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.6.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size.
Page 176: Valid Strobes
Upper data bus Lower data bus D8 D7 Byte size · Even address Byte size · Odd address Word size Longword 1st bus cycle size 2nd bus cycle Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) 6.6.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces.
Page 177: Basic Timing
6.6.3 Basic Timing 8-Bit 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle φ...
Page 178: Figure 6.11 Bus Timing For 8-Bit 3-State Access Space (Except Area 6)
8-Bit 3-State Access Space (Except Area 6): Figure 6.11 shows the bus timing for an 8-bit 3- state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle φ...
Page 179: Figure 6.12 Bus Timing For Area 6
8-Bit 3-State Access Space (Area 6): Figure 6.12 shows the bus timing for area 6. When area 6 is accessed, the data bus cannot be used. Wait states cannot be inserted. Bus cycle Address bus Read Invalid D7 to D0 Invalid High (16-bit bus...
Page 180: Figure 6.13 Bus Timing For 16-Bit 2-State Access Space (1) (Even Address Byte Access)
16-Bit 2-State Access Space: Figures 6.13 to 6.15 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
Page 181: Figure 6.14 Bus Timing For 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
Bus cycle φ Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Note: n = 0 to 7 Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.
Page 182: Figure 6.15 Bus Timing For 16-Bit 2-State Access Space (3) (Word Access)
Bus cycle φ Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.
Page 183: Figure 6.16 Bus Timing For 16-Bit 3-State Access Space (1) (Even Address Byte Access)
16-Bit 3-State Access Space: Figures 6.16 to 6.18 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Page 184: Figure 6.17 Bus Timing For 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
Bus cycle φ Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Note: n = 0 to 7 Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.
Page 185: Figure 6.18 Bus Timing For 16-Bit 3-State Access Space (3) (Word Access)
Bus cycle φ Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.
Page 186: Wait Control
6.6.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T state and T...
Page 187: Figure 6.19 Example Of Wait State Insertion Timing
Figure 6.19 shows an example of wait state insertion timing. By program wait φ Address bus Read Data bus Read data Write Data bus Write data Note: indicates the timing of pin sampling. Figure 6.19 Example of Wait State Insertion Timing Rev.
Page 188: Burst Rom Interface
Burst ROM Interface With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.
Page 189: Figure 6.20 Example Of Burst Rom Access Timing (When Ast0 = Brsts1 = 1)
Full access Burst access φ Only lower address changed Address bus Data bus Read data Read data Read data Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Full access Burst access φ Address bus Only lower address changed Data bus Read data...
Page 190: Wait Control
6.7.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.6.4, Wait Control. Wait states cannot be inserted in a burst cycle.
Page 191: Idle Cycle
Idle Cycle When this LSI accesses external space, it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.
Page 192: Figure 6.23 Example Of Idle Cycle Operation (2)
Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ Address bus Address bus (area A) (area A) (area B) (area B) Data bus Data bus Data collision Long output floating time (a) Idle cycle not inserted (b) Idle cycle inserted (ICIS0 = 0) (Initial value ICIS0 = 1)
Page 193: Table 6.4 Pin States In Idle Cycle
Table 6.4 shows pin states in an idle cycle. Table 6.4 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 High impedance High High High High High Rev. 3.0, 10/02, page 135 of 686...
Page 194: Bus Release
Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. In external extended mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1.
Page 195: Figure 6.25 Bus-Released State Transition Timing
Figure 6.25 shows the timing for transition to the bus-released state. CPU cycle External bus released state cycle High impedance Address bus Address High impedance Data bus High impedance High impedance High impedance High impedance Minimum 1 state Low level of pin is sampled at rise of T state.
Page 196: Bus Arbitration
6.10 Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DMAC, and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
Page 197: External Bus Release Usage Note
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states).
Page 198 Rev. 3.0, 10/02, page 140 of 686...
Page 199: Section 7 Dma Controller
Section 7 DMA Controller This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. Features The features of the DMAC are listed below. • Choice of short address mode or full address mode •...
Page 200: Figure 7.1 Block Diagram Of Dmac
A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A Addres buffer TGI1A TGI2A Processor TXI0 RXI0 TXI1 MAR0A RXI1 IOAR0A Control logic ETCR0A MAR0B USB request signals IOAR0B ETCR0B DMAWER MAR1A DMATCR IOAR1A DMACR0A DMACR0B...
Page 201: Register Configuration
Register Configuration The DMAC registers are listed below. The DMAC register functions differs depending on the address modes: short address mode and full address mode. The DMAC register functions are described in each address mode. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0.
Page 202 • Memory address register 1A (MAR1A) • I/O address register 1A (IOAR1A) • Transfer count register 1A (ETCR1A) • Memory address register 1B (MAR1B) • I/O address register 1B (IOAR1B) • Transfer count register 1B (ETCR1B) • DMA write enable register (DMAWER) •...
Page 203: Register Descriptions
Register Descriptions 7.3.1 Memory Address Registers (MAR) • Short Address Mode MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR.
Page 204: Execute Transfer Count Register (Etcr)
7.3.3 Execute Transfer Count Register (ETCR) • Short Address Mode ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other.
Page 205: Dma Control Register (Dmacr)
(b) ETCRB ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. 7.3.4 DMA Control Register (DMACR) DMACR controls the operation of each DMAC channel. •...
Page 206 Bit Bit Name Initial Value R/W Description Repeat Enable: Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. RPE DTIE Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt)
Page 207 Bit Bit Name Initial Value R/W Description DTF3 Data Transfer Factor: DTF2 These bits select the data transfer factor (activation source). DTF1 0000: – DTF0 0001: Activated by A/D conversion end interrupt 0010: – 0011: – 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt...
Page 208 • Full Address Mode (DMACRA) Bit Bit Name Initial Value R/W Description DTSZ Data Transfer Size: Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer SAID Source Address Increment/Decrement: SAIDE Source Address Increment/Decrement Enable: These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Page 209 • Full Address Mode (DMACRB) Bit Bit Name Initial Value R/W Description  Reserved This bit can be read from or written to. DAID Destination Address Increment/Decrement: DAIDE Destination Address Increment/Decrement Enable: These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
Page 210 Bit Bit Name Initial Value R/W Description DTF3 Data Transfer Factor: DTF2 These bits select the data transfer factor (activation source). DTF1 In normal mode: DTF0 0000: – 0001: – 0010: – 0011: Activated by DREQ signal’s low level input from USB (USB request) 010*: –...
Page 211: Dma Band Control Register (Dmabcr)
7.3.5 DMA Band Control Register (DMABCR) DMABCR controls the operation of each DMAC channel. • Short Address Mode Bit Bit Name Initial Value R/W Description FAE1 Full Address Enable 1: Specifies whether channel 1 is to be used in short address mode or full address mode.
Page 212 Bit Bit Name Initial Value R/W Description DTA1B Data Transfer Acknowledge: DTA1A These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the DTA0B data transfer factor setting. DTA0A When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
Page 213 Bit Bit Name Initial Value R/W Description DTE1B Data Transfer Enable: DTE1A When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. DTE0B If the activation source is an internal interrupt, an interrupt DTE0A request is issued to the CPU or DTC.
Page 214 • Full Address Mode Bit Bit Name Initial Value R/W Description FAE1 Full Address Enable 1: Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel.
Page 215 Bit Bit Name Initial Value R/W Description DTA1 Data Transfer Acknowledge: Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
Page 216 Bit Bit Name Initial Value R/W Description DTME1 Data Transfer Master Enable 1: Together with the DTE bit, this bit controls enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel.
Page 217 Bit Bit Name Initial Value R/W Description DTE1 Data Transfer Enable 1: When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
Page 218 Bit Bit Name Initial Value R/W Description DTIE1B Data Transfer Interrupt Enable B: Enables or disables an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC.
Page 219: Dma Write Enable Register (Dmawer)
7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that only specific bits of DMACR for the specific channel and also DMABCR can be changed to prevent inadvertent changes being made to registers other than those for the channel concerned.
Page 220 Bit Bit Name Initial Value R/W Description 7 to – – Reserved These bits are always read as 0 and cannot be modified. WE1B Write Enable 1B Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR by the DTC. 0: Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR are disabled 1: Writes to all bits in DMACR1B, bits 11, 7, and 3 in...
Page 221: Operation
Operation 7.4.1 Transfer Modes Table 7.2 lists the DMAC modes. Table 7.2 DMAC Transfer Modes Transfer Mode Transfer Source Remarks • • Short Dual (1) Sequential mode TPU channel 0 to 2 Up to 4 channels can address address compare match/input operate (2) Idle mode mode...
Page 222: Sequential Mode
7.4.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR.
Page 223: Figure 7.3 Operation In Sequential Mode
Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N–1)) Where: L = Value set in MAR Address B N = Value set in ETCR Figure 7.3 Operation in Sequential Mode...
Page 224: Figure 7.4 Example Of Sequential Mode Setting Procedure
[1] Set each bit in DMABCRH. Sequential mode setting · Clear the FAE bit to 0 to select short address mode. · Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
Page 225: Idle Mode
7.4.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR.
Page 226: Repeat Mode
A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set. Figure 7.6 shows an example of the setting procedure for idle mode. [1] Set ech bit in DMABCRH. Idle mode setting ·...
Page 227: Table 7.5 Register Functions In Repeat Mode
Table 7.5 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation Source Destination Start address of Incremented/decrem address address transfer destination ented every transfer. register register or transfer source Initial setting is restored when value reaches H'0000 Destination Source...
Page 228: Figure 7.7 Operation In Repeat Mode
Address T Transfer IOAR 1 byte or word transfer performed in rewponse to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N–1)) Where: L = Value set in MAR Address B N = Value set in ETCR Figure 7.7 Operation in Repeat Mode...
Page 229: Figure 7.8 Example Of Repeat Mode Setting Procedure
Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 7.8 shows an example of the setting procedure for repeat mode.
Page 230: Normal Mode
7.4.5 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA.
Page 231: Figure 7.9 Operation In Normal Mode
Figure 7.9 illustrates operation in normal mode. Address T Transfer Address T Address B Address B Legend Address T Address T SAID DTSZ Address B + SAIDE · (–1) · (2 · (N–1)) DAID DTSZ Address B + DAIDE · (–1) ·...
Page 232: Figure 7.10 Example Of Normal Mode Setting Procedure
Figure 7.10 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. Normal mode setting · Set the FAE bit to 1 to select full address mode. · Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Page 233: Block Transfer Mode
7.4.6 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times.
Page 234: Figure 7.11 Operation In Block Transfer Mode (Blkdir = 0)
Figure 7.11 illustrates operation in block transfer mode when MARB is designated as a block area. Address T Address T 1st block Block area Transfer Address B Consecutive transfer of M bytes or words is performed in rewponse to one request 2nd block Nth block...
Page 235: Figure 7.12 Operation In Block Transfer Mode (Blkdir = 1)
Figure 7.12 illustrates operation in block transfer mode when MARA is designated as a block area. Address T Address T Block area 1st block Transfer Consecutive transfer Address B of M bytes or words is performed in rewponse to one request 2nd block Nth block...
Page 236: Figure 7.13 Operation Flow In Block Transfer Mode
Start (DTE = DTME = 1) Transfer request? Acquire bus Read address specified by MARA SAID · DTSZ MARA = MARA + SAIDE · (–1) Write to address specified by MARB DAID DTSZ MARB = MARB + DAIDE · (–1) ·...
Page 237: Figure 7.14 Example Of Block Transfer Mode Setting Procedure
Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.14 shows an example of the setting procedure for block transfer mode.
Page 238: Dmac Activation Sources
7.4.7 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode, as shown in table 7.8. Table 7.8 DMAC Activation Sources Full Address Mode Activation Short Address Block Transfer...
Page 239: Basic Dmac Bus Cycles
request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Activation by Auto-Request: Auto-request activation is performed by register setting only, and transfer continues to the end.
Page 240: Dmac Bus Cycles (Dual Address Mode)
7.4.9 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7.16 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read...
Page 241: Figure 7.17 Example Of Full Address Mode (Cycle Steal) Transfer
DMA read DMA write DMA read DMA write DMA read DMA write dead φ Address bus Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or DTC.
Page 242: Figure 7.19 Example Of Full Address Mode (Block Transfer Mode) Transfer
If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state.
Page 243: Figure 7.20 Example Of Dreq Level Activated Normal Mode Transfer
DREQ DREQ Pin Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ DREQ DREQ pin is selected to 1. Figure 7.20 shows an example of DREQ level activated normal mode transfer. Bus release read write release...
Page 244: Dmac Multi-Channel Operation
1 block transfer 1 block transfer release dead Bus release release read write read write Transfer Transfer Transfer Transfer Address bus source destination source destination DMA control Idle Read Write Dead Idle Read Write Dead Idle Request clear period Request clear period Channel Request Request...
Page 245: Relation Between The Dmac, External Bus Requests, Refresh Cycles, And The Dtc
Table 7.9 DMAC Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0 High Channel 0B Channel 1A Channel 1 Channel 1B If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest- priority channel from among those issuing a request according to the priority order shown in table 7.14.
Page 246: Nmi Interrupts And Dmac
In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release.
Page 247: Forced Termination Of Dmac Operation
7.4.13 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again.
Page 248: Figure 7.25 Example Of Procedure For Clearing Full Address Mode
[1] Clear both the DTE bit and the DTME bit in Clearing full DMABCRL to 0; or wait until the transfer ends address mode and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time.
Page 249: Interrupts
Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.10 shows the interrupt sources and their priority order. Table 7.10 Interrupt Source Priority Order Interrupt Source Interrupt Interrupt Name Short Address Mode Full Address Mode Priority Order DEND0A Interrupt due to end of transfer...
Page 250: Usage Notes
Usage Notes 7.6.1 DMAC Register Access during Operation Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
Page 251: Module Stop
CPU longword read DMA transfer cycle MAR upper MAR lower word read word read DMA read DMA write DMA internal Transfer Transfer source destination address DMA control Idle Read Write Idle DMA register operation Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.28 Contention between DMAC Register Update and CPU Read 7.6.2 Module Stop...
Page 252: Internal Interrupt After End Of Transfer
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ signal low level remaining from the end of the previous transfer, etc. 7.6.5 Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1.
Page 253: Section 8 Data Transfer Controller (Dtc)
Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1.
Page 254: Register Descriptions
Internal address bus On-chip Interrupt controller Interrupt request DTCERA DTCERF CPU interrupt Internal data bus request Legend : DTC mode registers A and B MRA, MRB : DTC transfer count registers A and B CRA, CRB : DTC source address register : DTC destination address register : DTC enable registers A to G DTCERA to DTCERG...
Page 255: Dtc Mode Register A (Mra)
8.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Name Initial Value Description Undefined – Source Address Mode 1 and 0 Undefined – These bits specify an SAR operation after a data transfer. 0x: SAR is fixed 10: SAR is incremented after a transfer (by + 1 when Sz = 0;...
Page 256: Dtc Mode Register B (Mrb)
8.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Name Initial Value Description CHNE Undefined – DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 8.5.4, Chain Transfer.
Page 257: Dtc Transfer Count Register B (Crb)
bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 8.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode.
Page 258: Dtc Vector Register (Dtvecr)
8.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Name Initial Value Description SWDTE DTC Software Activation Enable Setting this bit to 1 activates DTC. The write value should always be 1.
Page 259: Activation Sources
Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared.
Page 260: Location Of Register Information And Dtc Vector Table
Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information.
Page 261: Figure 8.4 Correspondence Between Dtc Vector Address And Register Information
DTC vector Register information Register information address start address Chain transfer Figure 8.4 Correspondence between DTC Vector Address and Register Information Rev. 3.0, 10/02, page 203 of 686...
Page 262: Table 8.2 Interrupt Sources, Dtc Vector Addresses, And Corresponding Dtce
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCE Interrupt Origin of Vector DTC Vector Source Interrupt Source Number Address DTCE* Priority Software Write to DTVECR DTVECR H'0400 + (vector High number × 2) External pins IRQ0 H’0420 DTCEA7 IRQ1 H’0422 DTCEA6...
Page 263: Operation
Operation Register information is stored in an on-chip memory. When activated, the DTC reads register information in an on-chip memory and transfers data. After the data transfer, it writes updated register information back to the memory. Pre-storage of register information in the memory makes it possible to transfer data over any required number of channels.
Page 264: Normal Mode
Table 8.3 Overview of DTC Functions Address Register Transfer Mode Activation Source Source Destination Normal mode 24 bits 24 bits • TGI for TPU One byte or one word data is transferred in response to a single transfer request. CMI for 8-bit timer •...
Page 265: Figure 8.6 Memory Mapping In Normal Mode
Table 8.4 Register Information in Normal Mode Name Abbreviation Function DTC source address register Designates source address DTC destination address Designates destination address register DTC transfer count register A Designates transfer count DTC transfer count register B Not used Transfer Figure 8.6 Memory Mapping in Normal Mode Rev.
Page 266: Repeat Mode
8.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 8.5 lists the register information in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Page 267: Block Transfer Mode
8.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 8.6 lists the register information in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
Page 268: Chain Transfer
8.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the memory map for chain transfer.
Page 269: Interrupts
8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Page 270: Number Of Dtc Execution States
φ DTC activation request request Data transfer Vector read Read Write Read Write Address Transfer Transfer information read information write Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) φ DTC activation request request Data transfer Data transfer Vector read...
Page 271: Table 8.7 Dtc Execution Status
Table 8.7 DTC Execution Status Register information Internal Vector Read Read/Write Data read Data Write Operations Mode Normal Repeat Block transfer Legend: N: Block size (initial setting of CRAH and CRAL) Table 8.8 Number of States Required for Each Execution Status Chip Chip On-Chip I/O...
Page 272: Procedures For Using Dtc
Procedures for Using DTC 8.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3.
Page 273: Examples Of Use Of The Dtc
Examples of Use of the DTC 8.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).
Page 274: Usage Notes
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6.
Page 275: Section 9 I/O Ports
Section 9 I/O Ports Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
Page 276: Table 9.1 Port Functions (2)
Table 9.1 Port Functions (2) Input/Output Port Description Modes 4 and 5 Mode 6 Mode 7* Type Port 7 General I/O port P74/MRES P74/MRES also functioning P73/TMO1/CS7 P73/TMO1 as bus control P72/TMO0/CS6* P72/TMO0 output pins, P71/CS5 manual reset input pin, and 8- P70/TMRI01/TMCI01/CS4 P70/TMRI01/TMCI01 bit timer I/O...
Page 277: Table 9.1 Port Functions (3)
Table 9.1 Port Functions (3) Input/Output Port Description Modes 4 and 5 Mode 6 Mode 7* Type Port C General I/O port When DDR = 0: PC4 Built-in input also functioning pull-up MOS When DDR = 1: as address output pins When DDR = 0: PC3 When DDR = 1:...
Page 278: Table 9.1 Port Functions (4)
Table 9.1 Port Functions (4) Input/Output Port Description Modes 4 and 5 Mode 6 Mode 7* Type Port E General I/O port 8-bit bus mode: PE1 Built-in input also functioning pull-up MOS 16-bit bus mode: D1 as address output 8-bit bus mode: PE0 pins 16-bit bus mode: D0 Port F...
Page 279: Port 1
Port 1 Port 1 is an 8-bit I/O port. The port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 register (PORT1) 9.1.1 Port 1 Data Direction Register (P1DDR) P1DR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1.
Page 280: Port 1 Register (Port1)
9.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. Bit Name Initial Value Description * If a port 1 read is performed while P1DDR bits are set to 1, the P1DR value is read. If a port 1 read is performed * while P1DDR bits are cleared to 0, the pin states are read.
Page 281: Table 9.4 P15 Pin Function
Table 9.4 P15 Pin Function FADSEL of UCTLR − − − − TPU Channel 1 Setting Output Input or Initial Value − − P15DDR Pin function TIOCB1 output P15 input P15 output FSE0 output* TIOCB1 input TCLKC input Table 9.5 P14 Pin Function TPU Channel 1 Setting Output...
Page 282: Port 3
Table 9.7 P12 Pin Function AE3 to AE0 Other than B’1111 B’1111 − FADSEL of UCTLR* − − TPU Channel 0 Setting* Output Input or Initial Value − − − P12DDR Pin function TIOCC0 P12 input P12 output RCV input* A22 output output TIOCC0 input...
Page 283: Port 3 Data Direction Register (P3Ddr)
• Port 3 register (PORT3) • Port 3 open-drain control register (P3ODR) 9.2.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. Bit Name Initial Value Description − −...
Page 284: Port 3 Register (Port3)
9.2.3 Port 3 Register (PORT3) PORT3 shows the pin states. It cannot be written to. Writing of output data for the port 3 pins (P36 to P30) must always be performed on P3DR. Bit Name Initial Value Description − − Undefined Reserved This bit is undefined and cannot be modified.
Page 285: Pin Functions
9.2.5 Pin Functions Port 3 pins also function as SCI I/O pins and external interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are shown below. Table 9.10 P36 Pin Function P36DDR Pin function P36 input P36 output Table 9.11 P35 Pin Function CKE1 −...
Page 286: Port 4
Table 9.15 P31 Pin Function − P31DDR Pin function P31 input P31 output RxD0 input Table 9.16 P30 Pin Function − P30DDR Pin function P30 input P30 output TxD0 output Port 4 Port 4 is a 4-bit I/O port also functioning as A/D converter analog input. Port 4 has the following register.
Page 287: Port 7
Port 7 Port 7 is a 5-bit I/O port also functioning as bus control output, manual reset input, and 8-bit timer I/O. Port 7 has the following registers. • Port 7 data direction register (P7DDR) • Port 7 data register (P7DR) •...
Page 288: Port 7 Register (Port7)
9.4.3 Port 7 Register (PORT7) PORT7 shows the pin states. Bit Name Initial Value Description − − 7 to Undefined* Reserved These bits are undefined and cannot be modified. − If a port 7 read is performed while P7DDR bits are set to −...
Page 289: Table 9.19 P72 Pin Function
Table 9.19 P72 Pin Function Operating Mode Modes 4 to 6 Mode 7 − − − OS0 are all 0s At least OS0 are all 0 At least one one of − − is 1 is 1 − − P72DDR P72 input CS6 output Pin function TMO0...
Page 290: Port 9
Port 9 Port 9 pins also function as A/D converter analog input and D/A converter analog output pins. The port 9 has the following register. • Port 9 register (PORT9) 9.5.1 Port 9 Register (PORT9) PORT9 shows port 9 pin states. Bit Name Initial Value Description −...
Page 291: Port A Data Direction Register (Paddr)
9.6.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. Bit Name Initial Value Description − − 7 to Undefined Reserved These bits are undefined and cannot be modified. PA3DDR 0 Mode 7: Setting a PADDR bit to 1 makes the corresponding port A...
Page 292: Port A Register (Porta)
9.6.3 Port A Register (PORTA) PORTA shows port A pin states. Bit Name Initial Value Description − − 7 to Undefined Reserved These bits are undefined and cannot be modified. − If a port A read is performed while PADDR bits are set to −...
Page 293: Port A Open Drain Control Register (Paodr)
9.6.5 Port A Open Drain Control Register (PAODR) PAODR specifies an output type of port A. PAODR is valid for port output and SCI output pins. Bit Name Initial Value Description − − 7 to Undefined Reserved These bits are undefined and cannot be modified. PA3ODR 0 Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output pin, while clearing the bit...
Page 294: Table 9.23 Pa2 Pin Function
Operating mode Mode 7 AE3 to AE0 – FADSEL of UCTLR* CKE1 – – – CKE0 – – – PA3DDR – – – – Pin function SCK2 SCK2 SCK2 SUSPND input output output output input output* Note: * On-chip USB cannot be used in mode 7. Table 9.23 PA2 Pin Function Operating mode Modes 4 to 6...
Page 295: Port A Input Pull-Up Mos Function
9.6.7 Port A Input Pull-Up MOS Function Port A has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be specified as on or off for individual bits. Table 9.26 summarizes the input pull-up MOS states. Table 9.26 Input Pull-Up MOS States (Port A) Pins Power-On...
Page 296: Port B Data Direction Register (Pbddr)
9.7.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. Bit Name Initial Value Description PB7DDR 0 Mode 7: Setting a PBDDR bit to 1 makes the corresponding port B PB6DDR 0 pin an output port, while clearing the bit to 0 makes the PB5DDR 0...
Page 297: Port B Register (Portb)
9.7.3 Port B Register (PORTB) PORTB shows port B pin states. Bit Name Initial Value Description –* If the port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is –* performed while PBDDR bits are cleared to 0, the pin –*...
Page 298: Pin Functions
9.7.5 Pin Functions Port B pins also function as address output pins. The correspondence between the register specification and the pin functions is shown below. Table 9.27 PB7 Pin Function Operating mode Modes 4 to 6 Mode 7 − AE3 to AE0 Other than B’1xxx B’1xxx −...
Page 299: Port B Input Pull-Up Mos Function
Table 9.31 PB3 Pin Function Operating mode Modes 4 to 6 Mode 7 − AE3 to AE0 B’00xx Other than B’00xx − PB3DDR Pin function PB3 input PB3 output A11 output PB3 input PB3 output Table 9.32 PB2 Pin Function Operating mode Modes 4 to 6 Mode 7...
Page 300: Table 9.35 Input Pull-Up Mos States (Port B)
Table 9.35 Input Pull-Up MOS States (Port B) Pins Power-On Hardware Manual Software In Other Reset Standby Reset Standby Operations Mode Mode Address output, port output Port input ON/OFF Legend: OFF: Input pull-up MOS is always off. ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off. Rev.
Page 301: Port C
Port C Port C is an 8-bit I/O port that also has address bus (A7 to A0) output pins. The port C has the following registers. • Port C data direction register (PCDDR) • Port C data register (PCDR) • Port C register (PORTC) •...
Page 302: Port C Register (Portc)
9.8.3 Port C Register (PORTC) PORTC shows port C pin states. Bit Name Initial Value Description − If a port C read is performed while PCDDR bits are set to − 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin −...
Page 303: Table 9.37 Pc6 Pin Function
Table 9.37 PC6 Pin Function Operating Mode Modes 4 and 5 Mode 6 Mode 7 − PC6DDR Pin Function A6 output A6 output PC6 input PC6 output PC06 input Table 9.38 PC5 Pin Function Operating Mode Modes 4 and 5 Mode 6 Mode 7 −...
Page 304: Port C Input Pull-Up Mos Function
Table 9.43 PC0 Pin Function Operating Mode Modes 4 and 5 Mode 6* Mode 7 − PC0DDR Pin Function A0 output A0 output PC0input PC0 output PC00 input Note: * When on-chip USB is used in mode 6, bits PC7DDR to PC0DDR should be set to H’FF so that the pins output A7 to A0.
Page 305: Port D Data Direction Register (Pdddr)
9.9.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. Bit Name Initial Value Description PD7DDR 0 Modes 4 to 6: Port D pins automatically function as data input/output PD6DDR 0 pins.
Page 306: Port D Register (Portd)
9.9.3 Port D Register (PORTD) PORTD shows port D pin states. Bit Name Initial Value Description −* If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is −* performed while PDDDR bits are cleared to 0, the pin −*...
Page 307: Table 9.45 Pd7 Pin Function
Table 9.45 PD7 Pin Function Operating Mode Modes 4 and 6 Mode 7 − PD7DDR Pin Function D15 input/output PD7 input PD7 output Table 9.46 PD6 Pin Function Operating Mode Modes 4 and 6 Mode 7 − PD6DDR Pin Function D14 input/output PD6 input PD6 output...
Page 308: Port D Input Pull-Up Mos Function
Table 9.51 PD1 Pin Function Operating Mode Modes 4 and 6 Mode 7 − PD1DDR Pin Function D9 input/output PD1 input PD1 output Table 9.52 PD0 Pin Function Operating Mode Modes 4 and 6 Mode 7 − PD0DDR Pin Function D8 input/output PD0 input PD0 output...
Page 309: Port E Data Direction Register (Peddr)
9.10.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E. Bit Name Initial Value Description PE7DDR 0 Modes 4 to 6: When 8-bit bus mode is selected, port E functions as an PE6DDR 0 I/O port.
Page 310: Port E Register (Porte)
9.10.3 Port E Register (PORTE) PORTE shows port E pin states. Bit Name Initial Value Description −* If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed −* while PEDDR bits are cleared to 0, the pin states are −*...
Page 311: Pin Functions
9.10.5 Pin Function Port E pins also functions as data bus (D7 to D0) I/O. The correspondence between the register specification and the pin function in show below. Table 9.54 PE7 Pin Function Operating Mode Modes 4 to 6 Mode 7 −...
Page 312: Port E Input Pull-Up Mos State
Table 9.58 PE3 Pin Function Operating Mode Modes 4 to 6 Mode 7 − Bus Mode 8-bit bus mode 16-bit bus mode − PE3DDR Pin Function PE3 output PE3 input PE3 output PE3 input input/output Table 9.59 PE2 Pin Function Operating Mode Modes 4 to 6 Mode 7...
Page 313: Port F
Table 9.62 summarizes the input pull-up MOS states. Table 9.62 Input Pull-Up MOS States (Port E) Pins Power-On Hardware Manual Software In Other Reset Standby Reset Standby Operations Mode Mode Data output (16-bit bus mode in modes 4 to 6), port output (8-bit bus mode in modes 4 to 6 or mode 7)
Page 314: Port F Data Direction Register (Pfddr)
9.11.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. Bit Name Initial Value Description PF7DDR 1/0* Modes 4 to 6: Pin PF7 functions as the φ output pin when the PF6DDR 0 corresponding PFDDR bit is set to 1, and as an input port PF5DDR 0...
Page 315: Port F Register (Portf)
9.11.3 Port F Register (PORTF) PORTF shows port F pin states. Bit Name Initial Value Description −* If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed −* while PFDDR bits are cleared to 0, the pin states are −*...
Page 316: Table 9.66 Pf4 Pin Function
Table 9.66 PF4 Pin Function Operating Mode Modes 4 to 6 Mode 7 − PF4DDR HWA output Pin function PF4 input PF4 output Table 9.67 PF3 Pin Function Operating Mode Modes 4 to 6 Mode 7 − Bus Mode 16 bits 8 bits −...
Page 317: Port G
Table 9.70 PF0 Pin Function Operating Mode Modes 4 to 6 Mode 7 − BRLE − PF0DDR BREQ input Pin function PF0 input PF0 output PF0 input PF0 output IRQ2 input* Notes: * When used as an external interrupt input pin, do not use as an I/O pin for another function. 9.12 Port G Port G is a 5-bit I/O port that also has functioning as external interrupt input (IRQ7).and bus...
Page 318: Port G Data Register
9.12.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Name Initial Value Description − − 7 to Undefined Reserved These bits are undefined and cannot be modified. PG4DR An output data for a pin is stored when the pin function specified to a general purpose output port.
Page 319: Table 9.72 Pg3 Pin Function
Table 9.72 PG3 Pin Function Operating Mode Modes 4 to 6 Mode 7 PG3DDR CS1 output Pin function PG3 input PG3 input PG3 output Table 9.73 PG2 Pin Function Operating Mode Modes 4 to 6 Mode 7 PG2DDR CS2 output Pin function PG2 input PG2 input...
Page 320 Rev. 3.0, 10/02, page 262 of 686...
Page 321: Section 10 16-Bit Timer Pulse Unit (Tpu)
Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively.
Page 322: Figure 10.1 Block Diagram Of Tpu
Clock input φ/1 Internal clock: φ/4 φ/16 φ/64 φ/256 Internal data bus φ/1024 A/D converter convertion start signal External clock: TCLKA TCLKB TCLKC TCLKD Input/output pins Interrupt request signals Channel 0: TGI0A Channel 0: TIOCA0 TGI0B TIOCB0 TGI0C TIOCC0 TGI0D TIOCD0 TCI0V Channel 1:...
Page 323: Table 10.1 Tpu Functions
Table 10.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Count clock ø/1 ø/1 ø/1 ø/4 ø/4 ø/4 ø/16 ø/16 ø/16 ø/64 ø/64 ø/64 TCLKA ø/256 ø/1024 TCLKB TCLKA TCLKA TCLKC TCLKB TCLKB TCLKD TCLKC General registers TGRA_0 TGRA_1 TGRA_2 TGRB_0 TGRB_1...
Page 324 Item Channel 0 Channel 1 Channel 2 DTC activation TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture A/D converter trigger TGRA_0 compare TGRA_1 compare TGRA_2 compare match or input capture match or input capture match or input capture PPG trigger...
Page 325: Input/Output Pins
10.2 Input/Output Pins Table 10.2 Pin Configuration Channel Symbol Function TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin...
Page 326: Register Descriptions
10.3 Register Descriptions The TPU has the following registers. • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control register H_0 (TIORH_0) • Timer I/O control register L_0 (TIORL_0) • Timer interrupt enable register_0 (TIER_0) • Timer status register_0 (TSR_0) •...
Page 327: Timer Control Register (Tcr)
10.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel (channels 0 to 2). TCR register settings should be made only when TCNT operation is stopped. Bit Name Initial value Description CCLR2...
Page 328: Table 10.3 Cclr2 To Cclr0 (Channel 0)
Table 10.3 CCLR2 to CCLR0 (channel 0) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter coearing for another channel performing synchronous/clearing synchronous operation*...
Page 329: Table 10.5 Tpsc2 To Tpsc0 (Channel 0)
Table 10.5 TPSC2 to TPSC0 (channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 330: Table 10.7 Tpsc2 To Tpsc0 (Channel 2)
Table 10.7 TPSC2 to TPSC0 (channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024...
Page 331: Timer Mode Register (Tmdr)
10.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Name Initial value Description –...
Page 332: Timer I/O Control Register (Tior)
Table 10.8 MD3 to MD0 Bit 3 Bit2 Bit 1 Bit 0 Description MD3* MD2* Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 333 • • • • TIORL_0 Bit Name Initial value Description IOD3 I/O Control D3 to D0 IOD2 Specify the function of TGRD. IOD1 IOD0 IOC3 I/O Control C3 to C0 IOC2 Specify the function of TGRC. IOC1 IOC0 Rev. 3.0, 10/02, page 275 of 686...
Page 334: Table 10.9 Tiorh_0 (Channel 0)
Table 10.9 TIORH_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 TIOCB0 Pin Function IOB3 IOB2 IOB1 IOB0 Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 335: Table 10.10 Tiorh_0 (Channel 0)
Table 10.10 TIORH_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 TIOCA0 Pin Function IOA3 IOA2 IOA1 IOA0 Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 336: Table 10.11 Tiorl_0 (Channel 0)
Table 10.11 TIORL_0 (channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRA_0 TIOCD0 Pin Function IOD3 IOD2 IOD1 IOD0 Function Output Output disabled Compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 337: Table 10.12 Tiorl_0 (Channel 0)
Table 10.12 TIORL_0 (channel 0) Description Bit 3 Bit 2 Bit 1 Bit 1 TGRC_0 TIOCA0 Pin Function IOC3 IOC2 IOC1 IOC0 Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 338: Table 10.13 Tior_1 (Channel 1)
Table 10.13 TIOR_1 (channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 TIOCB1 Pin Function IOB3 IOB2 IOB1 IOB0 Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 339: Table 10.14 Tior_1 (Channel 1)
Table 10.14 TIOR_1 (channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 TIOCA0 Pin Function IOA3 IOA2 IOA1 IOA0 Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 340: Table 10.15 Tior_2 (Channel 2)
Table 10.15 TIOR_2 (channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 TIOCB2 Pin Function IOB3 IOB2 IOB1 IOB0 Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 341: Table 10.16 Tior_2 (Channel 2)
Table 10.16 TIOR_2 (channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 TIOCA2 Pin Function IOA3 IOA2 IOA1 IOA0 Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 342: Timer Interrupt Enable Register (Tier)
10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Bit Name Initial value Description TTGE A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Page 343 Bit Name Initial value Description TGIEB TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB disabled 1: Interrupt requests (TGIB) by TGFB enabled TGIEA TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the...
Page 344: Timer Status Register (Tsr)
10.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Bit Name Initial value Description TCFD Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 and 2.
Page 345 Bit Name Initial value Description TGFD R/(W) Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. The write value should always be 0 to clear this flag. In channels 1 and 2, bit 3 is reserved.
Page 346: Timer Counter (Tcnt)
Bit Name Initial value Description TGFB R/(W) Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. The write value should always be 0 to clear this flag. [Setting conditions] · When TCNT = TGRB while TGRB is functioning as output compare register ·...
Page 347: Timer Start Register (Tstr)
TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD. 10.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Page 348: Timer Synchro Register (Tsyr)
10.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to Bit Name Initial Value Description 7 to –...
Page 349: Interface To Bus Master
10.4 Interface to Bus Master 10.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.2.
Page 350: Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ Tmdr (Lower 8 Bits)]
Internal data bus Module master Bus interface data bus TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ ↔ TMDR (Lower 8 Bits)] ↔ ↔ Internal data bus Module master Bus interface data bus TMDR Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ ↔...
Page 351: Operation
10.5 Operation 10.5.1 Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of free- running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Page 352: Figure 10.7 Free-Running Counter Operation
TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR.
Page 353: Figure 10.9 Example Of Setting Procedure For Waveform Output By Compare Match
Select initial value 0 output or 1 output, and Output selection compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin unit the first compare match occurs. Set the timing for compare match generation in Select waveform output mode TGR.
Page 354: Figure 10.11 Example Of Toggle Output Operation
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 10.11 Example of Toggle Output Operation Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Page 355: Synchronous Operation
Counter cleared by TIOCB TCNT value input (falling edge) H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.13 Example of Input Capture Operation 10.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting).
Page 356: Figure 10.14 Example Of Synchronous Operation Setting Procedure
Synchronous operation selection Set synchronous operation Synchronous presetting Synchronous clearing Set TCNT Clearing source generation channel? Select counter Set synchronous clearing source counter clearing Start count Start count <Synchronous presetting> <Counter clearing> <Synchronous clearing> Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.
Page 357: Buffer Operation
Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 10.15 Example of Synchronous Operation 10.5.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers.
Page 358: Figure 10.17 Input Capture Buffer Operation
• When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.17. Input capture signal Timer general...
Page 359: Figure 10.19 Example Of Buffer Operation (1)
TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 H'0200 H'0450 H'0520 TGRC_0 Transfer H'0200 H'0450 TGRA_0 TIOCA Figure 10.19 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC.
Page 360: Pwm Modes
10.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register.
Page 361: Figure 10.21 Example Of Pwm Mode Setting Procedure
Example of PWM Mode Setting Procedure: Figure 10.21 shows an example of the PWM mode setting procedure. Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 362: Figure 10.23 Example Of Pwm Mode Operation (2)
Figure 10.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
Page 363: Phase Counting Mode
TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA...
Page 364: Figure 10.25 Example Of Phase Counting Mode Setting Procedure
counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10.19 shows the correspondence between external clock pins and channels.
Page 365: Figure 10.26 Example Of Phase Counting Mode 1 Operation
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.26 Example of Phase Counting Mode 1 Operation Table 10.20 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKB (Channel 1) TCLKC (Channel 2) TCLKD (Channel 2) Operation...
Page 366: Figure 10.27 Example Of Phase Counting Mode 2 Operation
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 2 Operation Table 10.21 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKB (Channel 1) TCLKC (Channel 2) TCLKD (Channel 2) Operation...
Page 367: Figure 10.28 Example Of Phase Counting Mode 3 Operation
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.28 Example of Phase Counting Mode 3 Operation Table 10.22 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKB (Channel 1) TCLKC (Channel 2) TCLKD (Channel 2) Operation...
Page 368: Figure 10.29 Example Of Phase Counting Mode 4 Operation
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.29 Example of Phase Counting Mode 4 Operation Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKB (Channel 1) Operation TCLKC (Channel 2) TCLKD (Channel 2)
Page 369: Interrupts
10.6 Interrupts 10.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 370: Dtc Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channel 0, and two each for channels 1 and 2.
Page 371: Operation Timing
10.7 Operation Timing 10.7.1 Input/Output Timing TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT input clock TCNT Figure 10.30 Count Timing in Internal Clock Operation φ...
Page 372: Figure 10.32 Output Compare Output Timing
φ TCNT input clock TCNT Compare match signal TIOC pin Figure 10.32 Output Compare Output Timing Input Capture Signal Timing: Figure 10.33 shows input capture signal timing. φ Input capture input Input capture signal TCNT Figure 10.33 Input Capture Input Signal Timing Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified.
Page 373: Figure 10.34 Counter Clear Timing (Compare Match)
φ Compare match signal Counter clear signal H'0000 TCNT Figure 10.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal H'0000 TCNT Figure 10.35 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 10.36 and 10.37 show the timing in buffer operation. φ...
Page 374: Interrupt Signal Timing
φ Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 10.37 Buffer Operation Timing (Input Capture) 10.7.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ...
Page 375: Figure 10.39 Tgi Interrupt Timing (Input Capture)
φ Input capture signal TCNT TGF flag TGI interrupt Figure 10.39 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 376: Figure 10.41 Tciu Interrupt Setting Timing
φ TCNT input clock TCNT H'0000 H'FFFF (underflow) Underflow signal TCFU flag TCIU interrupt Figure 10.41 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it.
Page 377: Figure 10.43 Timing For Status Flag Clearing By Dtc Or Dmac Activation
read cycle write cycle φ Destination Source address Address address Status flag Interrupt request signal Figure 10.43 Timing for Status Flag Clearing by DTC or DMAC Activation Rev. 3.0, 10/02, page 319 of 686...
Page 378: Usage Notes
10.8 Usage Notes Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 379: Figure 10.45 Contention Between Tcnt Write And Clear Operations
TCNT write cycle φ Address TCNT address Write signal Counter clear signal H'0000 TCNT Figure 10.45 Contention between TCNT Write and Clear Operations Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.46 shows the timing in this case.
Page 380: Figure 10.47 Contention Between Tgr Write And Compare Match
TGR write cycle φ TGR address Address Write signal Compare Inhibited match signal TCNT TGR write data Figure 10.47 Contention between TGR Write and Compare Match Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write.
Page 381: Figure 10.49 Contention Between Tgr Read And Input Capture
TGR read cycle φ TGR address Address Read signal Input capture signal Internal data bus Figure 10.49 Contention between TGR Read and Input Capture Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed.
Page 382: Figure 10.51 Contention Between Buffer Register Write And Input Capture
Buffer register write cycle φ Buffer register Address address Write signal Input capture signal TCNT Buffer register Figure 10.51 Contention between Buffer Register Write and Input Capture Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence.
Page 383: Figure 10.53 Contention Between Tcnt Write And Overflow
TCNT write cycle φ TCNT address Address Write signal TCNT write data TCNT H'FFFF TCFV flag Figure 10.53 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
Page 384 Rev. 3.0, 10/02, page 326 of 686...
Page 385: Section 11 8-Bit Timers (Tmr)
Section 11 8-Bit Timers (TMR) This LIS includes an 8-bit timer module with two channels. Each channel has an 8-bit counter and two registers that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle.
Page 386: Figure 11.1 Block Diagram Of 8-Bit Timer
External clock source Internal clock sources TMCI01 ø/8 ø/64 ø/8192 Clock 1 Clock select Clock 0 TCORA0 TCORA1 Compare match A1 Comparator A0 Comparator A1 Compare match A0 Overflow 1 TMO0 Overflow 0 TCNT0 TCNT1 TMRI01 Clear 0 Clear 1 Compare match B1 Comparator B0 Comparator B1...
Page 387: Input/Output Pins
11.2 Input/Output Pins Table 11.1 summarizes the input and output pins of the TMR. Table 11.1 Pin Configuration Channel Name Symbol Function Timer output pin 0 TMO0 Output Outputs at compare match Timer output pin 1 TMO1 Output Outputs at compare match 0,1 All Timer clock input pin 01 TMCI01...
Page 388 11.3.3 Time Constant Registers B (TCORB) The TCORB_0 registers are 8-bit readable/writable registers. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1.
Page 389 11.3.4 Time Control Registers (TCR) The TCR registers select the clock source and the time at which TCNT is cleared, and enable interrupts. Bit Name Initial Value Description CMIEB Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1.
Page 390: Timer Control/Status Registers (Tcsr)
Table 11.2 Clock Input to TCNT and Count Condition Channel Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description TMR_0 Clock input disabled Internal clock, counted at falling edge of ø/8 Internal clock, counted at falling edge of ø/64 Internal clock, counted at falling edge of ø/8192 Count at TCNT1 overflow signal* TMR_1...
Page 391 Bit Name Initial Value Description CMFB R/(W)* Compare Match Flag B [Setting condition] • Set when TCNT matches TCORB [Clearing conditions] (Initial value) • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 CMFA R/(W)* Compare Match Flag A...
Page 392: Operation
11.4 Operation 11.4.1 Pulse Output Figure 11.2 shows an example that the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: 1. In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared at a TCORA compare match.
Page 393: Operation Timing
11.5 Operation Timing 11.5.1 TCNT Incrementation Timing Figure 11.3 shows the count timing for internal clock input. Figure 11.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
Page 394: Setting Of Compare Match Flags Cmfa And Cmfb
11.5.2 Setting of Compare Match Flags CMFA and CMFB The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Page 395: Timing Of Tcnt External Reset
ø Compare match signal TCNT H'00 Figure 11.7 Timing of Compare Match Clear 11.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 11.8 shows the timing of this operation.
Page 396: Timing Of Overflow Flag (Ovf) Setting
11.5.6 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 11.9 shows the timing of this operation. ø TCNT H'FF H'00 Overflow signal Figure 11.9 Timing of OVF Setting Rev.
Page 397: Operation With Cascaded Connection
11.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode).
Page 398: Interrupts
11.7 Interrupts 11.7.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 11.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller.
Page 399: Usage Notes
11.8 Usage Notes 11.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 11.10 shows this operation.
Page 400: Contention Between Tcnt Write And Increment
11.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 11.11 shows this operation. TCNT write cycle by CPU ø...
Page 401: Contention Between Tcor Write And Compare Match
11.8.3 Contention between TCOR Write and Compare Match During the T state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs. In TMR, when ICR input capture and compare match event occur at the same time, the ICR input capture has priority and the compare match signal is inhibited.
Page 402: Contention Between Compare Matches A And B
11.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 11.4.
Page 403: Table 11.5 Switching Of Internal Clock And Tcnt Operation
Table 11.5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from Clock before low to low* switchover Clock after switchover TCNT clock TCNT CKS bit write Switching from Clock before low to high* switchover...
Page 404: Mode Setting With Cascaded Connection
Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock before Switching from high switchover to high Clock after switchover TCNT clock TCNT CKS bit write Notes:* 1 Includes switching from low to stop, and from stop to low. * 2 Includes switching from stop to high.
Page 405: Section 12 Watchdog Timer
Section 12 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer.
Page 406: Register Descriptions
12.2 Register Descriptions The WDT has the following three registers. For details, refer to section 23, List of Registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different method to normal registers. For details, refer to section 12.5.1, Notes on Register Access. •...
Page 407 Bit Name Initial Value Description R/(W)* Overflow Flag Indicates that TCNT has overflowed. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows (changes from H’FF to H’00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Page 408: Reset Control/Status Register (Rstcsr)
12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows.
Page 409: Operation
12.3 Operation 12.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
Page 410: Timing Of Setting Of Watchdog Timer Overflow Flag (Wovf)
12.3.2 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) With WDT0, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip.
Page 411: Interval Timer Mode
12.3.3 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. TCNT count Overflow Overflow Overflow Overflow H'FF Time H'00 WOVI...
Page 412: Interrupts
12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 12.1 WDT Interrupt Source Name Interrupt Source...
Page 413: Contention Between Timer Counter (Tcnt) Write And Increment
RSTCSR must be written to by a word transfer to address H'FF76. It cannot be written to with byte instructions. Figure 12.7 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the upper byte of the written word must contain H'A5 and the lower byte must contain H'00.
Page 414: Changing Value Of Cks2 To Cks0
TCNT write cycle Address Internal write signal TCNT input clock TCNT Counter write data Figure 12.8 Contention between TCNT Write and Increment 12.5.3 Changing Value of CKS2 to CKS0 If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in the incrementation.
Page 415: Section 13 Serial Communication Interface
Section 13 Serial Communication Interface This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Page 416: Block Diagram
• A multiprocessor communication function is provided that enables serial data communication with a number of processors Clocked Synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors detected • SCI select function (SCI_0): TxD0 = high-impedance and SCK0 = fixed high-level input can selected when IRQ7 = 1) •...
Page 417: Figure 13.1 Block Diagram Of Sci_0
Module data bus SCMR Baud rate RxD0 generator SEMR control TxD0 transmission and reception Detecting parity Parity Clock check PG1/ CKE1 Average transfer rate generator 10.667MHz · 115.152kbps External clock · 460.606kbps 16MHz SCK0 · 460.784kbps · 720kbps TIOCA1 TCLKA TIOCA2 Legend : Receive shift register...
Page 418: Figure 13.2 Block Diagram Of Sci_1 And Sci_2
Module data bus SCMR Baud rate generator control transmission and reception Clock Detecting parity Parity check External clock Legend : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register : Serial status register SCMR : Smart card register...
Page 419: Input/Output Pins
13.2 Input/Output Pins Table 13.1 shows the serial pins for each SCI channel. Table 13.1 Pin Configuration Channel Pin Name* Function SCK0 SCI_0 clock input/output RxD0 Input SCI_0 receive data input TxD0 Output SCI_0 transmit data output SCK1 SCI_1 clock input/output RxD1 Input SCI_1 receive data input...
Page 420: Receive Data Register (Rdr)
13.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled.
Page 421: Serial Mode Register (Smr)
13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source. Bit Name Initial Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length.
Page 422 Bit Name Initial Value Description CKS1 Clock Select 0 and 1: CKS0 These bits select the clock source for the baud rate generator. 00: ø clock (n = 0) 01: ø/4 clock (n = 1) 10: ø/16 clock (n = 2) 11: ø/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.10, Bit Rate Register...
Page 423: Serial Control Register (Scr)
13.3.6 Serial Control Register (SCR) SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, refer to section 13.8, Interrupts. Bit Name Initial Value Description Transmit Interrupt Enable...
Page 424 Bit Name Initial Value Description MPIE Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited.
Page 425: Serial Status Register (Ssr)
13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Bit Name Initial Value Description TDRE R/(W)* Transmit Data Register Empty...
Page 426 Bit Name Initial Value Description ORER R/(W)* Overrun Error [Setting condition] · When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1.
Page 427 Bit Name Initial Value Description TEND Transmit End [Setting conditions] · When the TE bit in SCR is 0 · When TDRE = 1 at transmission of the last bit of a 1- byte serial transmit character [Clearing conditions] · When 0 is written to TDRE after reading TDRE = 1 ·...
Page 428: Smart Card Mode Register (Scmr)
13.3.8 Smart Card Mode Register (SCMR) SCMR selects LSB-first or MSB-first by means of bit SDIR. In this LSI, smart card interface mode cannot be specified. Bit Name Initial Value Description 7 to 4 — — Reserved These bits are always read as 1. Smart Card Data Transfer Direction Selects the serial/parallel conversion format.
Page 429: Serial Extended Mode Register 0 (Semr_0)
13.3.9 Serial Extended Mode Register 0 (SEMR_0) SEMR_0 extends the functions of SCI_0. SEMR0 enables selection of the SCI_0 select function in synchronous mode, base clock setting in asynchronous mode, and also clock source selection and automatic transfer rate setting. Figure 13.3 shows an example of the internal base clock when an average transfer rate is selected.
Page 430 Bit Name Initial Value Description ACS2 Asynchronous Clock Source Select 2 to 0 ACS1 These bits select the clock source in asynchronous mode. When an average transfer rate is selected, the ACS0 base clock is set automatically regardless of the ABCS value.
Page 431: Figure 13.3 Examples Of Base Clock When Average Transfer Rate Is Selected
Figure 13.3 Examples of Base Clock when Average Transfer Rate is Selected Rev. 3.0, 10/02, page 373 of 686...
Page 432: Figure 13.4 Example Of Average Transfer Rate Setting With Tpu Clock Input
Figure 13.4 Example of Average Transfer Rate Setting with TPU Clock Input Rev. 3.0, 10/02, page 374 of 686...
Page 433: Bit Rate Register (Brr)
13.3.10 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
Page 434: Table 13.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1 Operating Frequency ø (MHz) 2.097152 2.4576 Error Error Error Error Bit Rate (bit/s) 0.03 –0.04 1 –0.26 1 0.03 0.16 –0.21 1 0.00 0.16 0.16 –0.21 0 0.00 0.16 0.16 –0.21 0 0.00...
Page 435: Table 13.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency ø (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bit/s) –0.44 2 0.08 –0.07 2 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200...
Page 436: Table 13.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (3)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency ø (MHz) 14.7456 Error Error Error Bit Rate (bit/s) –0.17 3 0.70 0.03 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16...
Page 437: Table 13.5 Maximum Bit Rate With External Clock Input (Asynchronous Mode)
Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Maximum Bit Rate External Maximum Bit Rate External (kbps) Input (kbps) Input ø (MHz) Clock ABCS=0 ABCS=1 Clock ABCS=0 ABCS=1 (MHz) (MHz) ø (MHz) 0.5000 31.5 62.5 7.3728 1.8432 115.2 230.4 2.097152 0.5243...
Page 438: Table 13.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency ø (MHz) Bit Rate (bit/s) — — — — — — — — 2.5k 100k 250k 500k 2.5M Legend Blank : Cannot be set. — : Can be set, but there will be a degree of error. : Continuous transfer is not possible.
Page 439: Operation In Asynchronous Mode
13.4 Operation in Asynchronous Mode Figure 13.5 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Page 440: Table 13.8 Serial Transfer Formats (Asynchronous Mode)
Table 13.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP...
Page 441: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 442: Clock
13.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Page 443: Data Transmission (Asynchronous Mode)
[1] Set the clock selection in SCR. Start initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 When the clock is selected in asynchronous mode, it is output Set CKE1 and CKE0 bits in SCR immediately after SCR settings are...
Page 444: Figure 13.9 Example Of Operation In Transmission In Asynchronous Mode (Example With 8-Bit Data, Parity, One Stop Bit)
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
Page 445: Figure 13.10 Sample Serial Transmission Flowchart
Figure 13.10 shows a sample flowchart for transmission in asynchronous mode. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 446: Serial Data Reception (Asynchronous Mode)
13.4.6 Serial Data Reception (Asynchronous Mode) Figure 13.11 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 447: Table 13.9 Ssr Status Flags And Receive Data Handling
Table 13.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception.
Page 448: Figure 13.12 Sample Serial Reception Data Flowchart (1)
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 449: Multiprocessor Communication Function
Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 13.12 Sample Serial Reception Data Flowchart (2) 13.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of...
Page 450: Multiprocessor Serial Data Transmission
differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 13.13 shows an example of inter-processor communication using the multiprocessor format.
Page 451: Figure 13.14 Sample Multiprocessor Serial Transmission Flowchart
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR...
Page 452: Multiprocessor Serial Data Reception
13.5.2 Multiprocessor Serial Data Reception Figure 13.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 453: Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (1)
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. Read MPIE bit in SCR [3] SCI status check, ID reception and Read ORER and FER flags in SSR comparison: Read SSR and check that the RDRF...
Page 454: Operation In Clocked Synchronous Mode
Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 13.16 Sample Multiprocessor Serial Reception Flowchart (2) 13.6 Operation in Clocked Synchronous Mode Figure 13.17 shows the general format for clocked synchronous communication.
Page 455: Clock
One unit of transfer data (character or frame) Synchronization clock Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Serial data Don’t care Don’t care Note: * High except in continuous transfer Figure 13.17 Data Format in Synchronous Communication (For LSB-First) 13.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external...
Page 456: Serial Data Transmission (Clocked Synchronous Mode)
[1] Set the clock selection in SCR. Be sure Start initialization to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR.
Page 457: Figure 13.19 Sample Sci Transmission Operation In Clocked Synchronous Mode
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6.
Page 458: Serial Data Reception (Clocked Synchronous Mode)
[1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin. [2] SCI status check and transmit data Read TDRE flag in SSR write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Page 459: Figure 13.21 Example Of Sci Operation In Reception
generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished. Synchronization clock Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data RDRF...
Page 460: Figure 13.22 Sample Serial Reception Flowchart
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 461: Simultaneous Serial Data Transmission And Reception
13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 13.23 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Page 462: Figure 13.23 Sample Flowchart Of Simultaneous Serial Transmit And Receive Operations
[1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data Start transmission/reception input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE...
Page 463: Sci Select Function
13.7 SCI Select Function The SCI_0 supports the SCI select function which allows clock synchronous communication between master LSI and one of multiple slave LSI. Figure 13.24 shows an example of communication using the SCI select function. Figure 13.25 shows the operation. The master LSI can communicate with slave LSI_A by bringing SEL_A and SEL_B signals low and high, respectively.
Page 464: Figure 13.24 Example Of Communication Using The Sci Select Function
Master LSI Slave LSI_A (This LSI) Interrupt controller RxD0_A M_TxD RSR0_A TSR0_A TxD0_A M_RxD Transmission/ SCK0_A SCK0 reception M_SCK control C/A=CKE1=SSE=1 Slave LSI_B (This LSI) RxD0_B TxD0_B SCK0_B SCK0 Note: * The selection signals (SEL_A and SEL_B) of the LSI must be switched while the serial clock (M_SCK) is high after the end bit of the transmit data has been send.
Page 465: Figure 13.25 Operation Of Communication Using The Sci Select Function
Communication between master LSI and slave LSI_A Communication between master LSI and slave LSI_B Master LSI Period of M_SCK = high* M_SCK M_TxD M_RxD Slave LSI_A SCK0_A Fixed high level RSR0_A Hi-Z Hi-Z TxD0_A Slave LSI_B Fixed high level SCK0_B RSR0_B Hi-Z Hi-Z...
Page 466: Interrupts
13.8 Interrupts 13.8.1 Interrupts in Normal Serial Communication Interface Mode Table 13.10 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Page 467: Usage Notes
Table 13.10 SCI Interrupt Sources DMAC Channel Name Interrupt Source Interrupt Flag Activation Activation Priority* ERI0 Receive Error ORER, FER, PER Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empty TDRE Possible Possible TEI0 Transmission End TEND...
Page 468: Receive Error Flags And Transmit Operations (Clocked Synchronous Mode Only)
13.9.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission.
Page 469: Figure 13.27 Sample Flowchart For Mode Transition During Transmission
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode, software standby mode, or subsleep mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission.
Page 470: Figure 13.28 Port Pin State Of Asynchronous Transmission Using Internal Clock
Transition Exit from End of to software software Start of transmission transmission standby standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 13.28 Port Pin State of Asynchronous Transmission Using Internal Clock Transition...
Page 471: Switching From Sck Pin Function To Port Pin Function
<Reception> Read RDRF flag in SSR Receive data being received RDRF= 1 becomes invalid. Read receive data in RDR RE= 0 Transition to software Includes module stop mode. standby mode, etc. Exit from software standby mode, etc. Change operating mode? Initialization RE= 1 <Start of reception>...
Page 472: Figure 13.31 Operation When Switching From Sck Pin Function To Port Pin Function
Half-cycle low-level output SCK/port 1. End of transmission 4. Low-level output Data Bit 6 Bit 7 2.TE= 0 3.C/A= 0 CKE1 CKE0 Figure 13.31 Operation when Switching from SCK Pin Function to Port Pin Function Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit.
Page 473: Figure 13.32 Operation When Switching From Sck Pin Function To Port Pin Function (Example Of Preventing Low-Level Output)
High-level output SCK/port 1. End of transmission Bit 6 Bit 7 Data 2.TE= 0 4.C/A= 0 3.CKE1= 1 5.CKE1= 0 CKE1 CKE0 Figure 13.32 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev.
Page 474 Rev. 3.0, 10/02, page 416 of 686...
Page 475: Section 14 Boundary Scan Function
Section 14 Boundary Scan Function This LSI incorporates a boundary scan function, which is a serial I/O interface based on the JTAG (Joint Test Action Group, IEEEStd.1149.1 and IEEE Standard Test Access Port and Boundary Scan Architecture). Figure 14.1 shows the block diagram of the boundary scan function. 14.1 Features •...
Page 476: Figure 14.1 Block Diagram Of Boundary Scan Function
BSCANR (Boundary scan cell chain) IDCODE BYPASS INSTR TAP controller Legend: BSCANR : Boundary scan register IDCODE : IDCODE register BYPASS : BYPASS register INSTR : Instruction register :Test access port Figure 14.1 Block Diagram of Boundary Scan Function Rev. 3.0, 10/02, page 418 of 686...
Page 477: Pin Configuration
14.2 Pin Configuration Table 14.1 shows the I/O pins used in the boundary scan function. Table 14.1 Pin Configuration Pin Name Function Input Test Mode Select Controls the TAP controller which is a 16-state Finite State Machine. The TMS input value at the rising edge of TCK determines the status transition direction on the TAP controller.
Page 478: Register Descriptions
14.3 Register Descriptions The boundary scan function has the following registers. These registers cannot be accessed by the CPU. • Instruction register (INSTR) • IDCODE register (IDCODE) • BYPASS register (BYPASS) • Boundary scan register (BSCANR) 14.3.1 Instruction Register (INSTR) INSTR is a 3-bit register.
Page 479 (1) EXTEST The EXTEST instruction is used to test external circuits when this LSI is installed on the print circuit board. If this instruction is executed, output pins are used to output test data (specified by the SAMPLE/PRELOAD instruction) from the boundary scan register to the print circuit board, and input pins are used to input test results.
Page 480: Idcode Register (Idcode)
14.3.2 IDCODE Register (IDCODE) IDCODE is a 32-bit register. If INSTR is set to IDCODE mode, IDCODE is connected between TDI and TDO. The HD64F2215, HD64F2215U, HD6432215A, HD6432215B, and HD6432215C output fixed codes H’0002200F, H’0003200F, H’001B200F, and H’001C200F, respectively, from the TDO.
Page 481: Figure 14.2 Boundary Scan Register Configuration
TDI pin Control I/O pin TDO pin Figure 14.2 Boundary Scan Register Configuration Rev. 3.0, 10/02, page 423 of 686...
Page 482: Table 14.4 Correspondence Between Lsi Pins And Boundary Scan Register
Table 14.4 Correspondence between LSI Pins and Boundary Scan Register TFP-120 BP-112 Pin No. Pin No. Pin Name Bit Name From TDI PE0/D0 Control PE1/D1 Control PE2/D2 Control PE3/D3 Control PE4/D4 Control PE5/D5 Control PE6/D6 Control PE7/D7 Control PD0/D8 Control PD1/D9 Control Rev.
Page 483 TFP-120 BP-112 Pin No. Pin No. Pin Name Bit Name PD2/D10 Control PD3/D11 Control PD4/D12 Control PD5/D13 Control PD6/D14 Control PD7/D15 Control PC0/A0 Control PC1/A1 Control PC2/A2 Control PC3/A3 Control PC4/A4 Control Rev. 3.0, 10/02, page 425 of 686...
Page 484 TFP-120 BP-112 Pin No. Pin No. Pin Name Bit Name PC5/A5 Control PC6/A6 Control PC7/A7 Control PB0/A8 Control PB1/A9 Control PB2/A10 Control PB3/A11 Control PB4/A12 Control PB5/A13 Control PB6/A14 Control PB7/A15 Control Rev. 3.0, 10/02, page 426 of 686...
Page 485 TFP-120 BP-112 Pin No. Pin No. Pin Name Bit Name PA0/A16 Control PA1/A17/TxD2 Control PA2/A18/RxD2 Control PA3/A19/SCK2/SUSPND Control P10/TIOCA0/A20/VM Control P11/TIOCB0/A21/VP Control P12/TIOCC0/TCLKA/A22/RCV Control P13/TIOCD0/TCLKB/A23/VPO Control P14/TIOCA1/IRQ0 Control P15/TIOCB1/TCLKC/FSE0 Control P16/TIOCA2/IRQ1 Control Rev. 3.0, 10/02, page 427 of 686...
Page 486 TFP-120 BP-112 Pin No. Pin No. Pin Name Bit Name P17/TIOCB2/TCLKD/OE Control USPND VBUS UBPM STBY PF7/φ Control PF6/AS Control PF5/RD Control PF4/HWR Control PF3/LWR/ADTRG/IRQ3 Control PF2/WAIT Control PF1/BACK Control Rev. 3.0, 10/02, page 428 of 686...
Page 487 TFP-120 BP-112 Pin No. Pin No. Pin Name Bit Name PF0/BREQ/IRQ2 Control P30/TxD0 Control P31/RxD0 Control P32/SCK0/IRQ4 Control P33/TxD1 Control P34/RxD1 Control P35/SCK1/IRQ5 Control Control P74/MRES Control P73/TMO1/CS7 Control P72/TMO0/CS6 Control Rev. 3.0, 10/02, page 429 of 686...
Page 488 TFP-120 BP-112 Pin No. Pin No. Pin Name Bit Name P71/CS5 Control P70/TMRI01/TMCI01/CS4 Control Control PG1/CS3/IRQ7 Control PG2/CS2 Control PG3/CS1 Control PG4/CS0 Control to TDO Rev. 3.0, 10/02, page 430 of 686...
Page 489: Boundary Scan Function Operation
14.4 Boundary Scan Function Operation 14.4.1 TAP Controller Figure 14.3 shows the TAP controller status transition diagram, based on the JTAG standard. Test-Logic-Reset Run-Test/Idle Select-DR Select-IR Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-IR Pause-DR Exit2-DR Update-DR Update-IR Exit2-IR Figure 14.3 TAP Controller Status Transition Note: The transition condition is the TMS value at the rising edge of TCK.
Page 490: Figure 14.4 Recommended Reset Signal Design
• TRST must be separated from the system circuitry in order not to affect the system operation. • System circuitry must also be separated from the TRST in order not to affect TRST operation as shown in figure 14.4. Board edge pin System reset Power-on...
Page 491: Section 15 Universal Serial Bus Interface (Usb)
Section 15 Universal Serial Bus Interface (USB) This LSI incorporates a USB function module complying with USB standard 1.1. Figure 15.1 shows the block diagram of the USB. 15.1 Features • USB standard version 1.1 compliant • Bus-powered mode or self-powered mode is selectable via the USB specific pin (UBPM) •...
Page 492 • Maximum Configuration, InterfaceNumber, and AlternateSetting configuration specifications of this LSI Configuration 1 ----- InterfaceNumber 0 to 2 ----- AlternateSetting 0 to 7 ----- EP0, EP1 to EP8 • Start of frame (SOF) marker function  SOF interrupt occurs every 1 ms even though broken SOF received by error •...
Page 493: Figure 15.1 Block Diagram Of Usb
[Power mode selection] 1288-byte FIFO EP0s EP2i EP4i [Connection/disconnection] EP0i EP2o EP4o VBUS EP0o EP3i EP5i [Suspend] EP1i EP3o USPND [Interrupt request signal] [Power supply] DrVcc DrVss [DMA internal request signal] [Data] Internal Registers transceiver [Internal bus] USD+ Peripheral data bus Interface USD- Peripheral address bus...
Page 494: Input/Output Pins
15.2 Input/Output Pins Table 15.1 shows the USB pin configuration. Table 15.1 Pin Configuration Pin Name Function USD+ I/O pin for USB data USD- DrVCC Input USB internal transceiver power supply pin DrVSS Input USB internal transceiver ground pin VBUS Input USB cable connection/disconnection detection signal pin UBPM...
Page 495: Register Descriptions
15.3 Register Descriptions The USB has the following registers for each channel. • USB endpoint information register 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4) • USB control register (UCTLR) • USB DMAC transfer request register (UDMAR)* • USB device resume register (UDRR) •...
Page 496: Usb Endpoint Information Registers 00_0 To 22_4 (Uepir00_0 To Uepir22_4)
• USB interrupt selection register 1 (UISR1)* • USB interrupt selection register 2 (UISR2)* • USB interrupt selection register 3 (UISR3) • USB data status register (UDSR)* • USB configuration value register (UCVR) • USB time stamp register H, L (UTSRH, L) •...
Page 497 • • • • UEPIRnn_0 Bit Name Initial Value Description 7 to D39 –D36 — Endpoint number (4-bit configuration, settable values: 0 to 8) 0000: Control transfer (EP0) 0001 to 1000: Other than Control transfer (EP1 to EP8) There are restrictions on settable endpoint numbers according to the Interface number and Alternate number to which the endpoint belongs.
Page 498 • • • • UEPIRnn_1 Bit Name Initial Value Description 7 to D31 –D29 — Alternate number to which endpoint belongs (3-bit configuration, settable values: 0 to 7) 000: Control transfer 001 to 111: Other than Control transfer — Endpoint transfer type (2-bit configuration) —...
Page 499 • • • • UEPIRnn_3 Bit Name Initial Value Description 7 to D15 –D8 — Endpoint internal address (D15 to D0 16-bit configuration) Set UEPIR00_3, UEPIR00_4 = H'0000 Set UEPIR01_3, UEPIR01_4 = H'0001 Set UEPIR21_3, UEPIR21_4 = H'0015 Set UEPIR22_3, UEPIR22_4 = H'0016 •...
Page 500: Figure 15.2 Example Of Endpoint Configuration Based On Bluetooth Standard
information is returned as 16 bytes while the maximum packet size of the EPINFO data is eight bytes, the host attempts to access the EPINFO data in 16 byte units and cannot operate correctly. EP0 Control(in,out) 64 bytes Configuration 1 InterfaceNumber 0 AlternateSetting 0 EP1i Interrupt(in) 16 bytes...
Page 501: Table 15.2 Epinfo Data Settings
Table 15.2 EPINFO Data Settings EPINFO Data Settings Based on Bluetooth Standard Register Corresponding UEPIRn_0 to UEPI UEPI UEPI UEPI UEPI Name Address Transfer Mode* UEPIRn_4 Settings Rn_0 Rn_1 Rn_2 Rn_3 Rn_3 Specific to B'0000_00_00_000_00_0_ H'00 H'00 H'40 H'00 H'00 UEPIR00_0 to H'C00000 UEPIR00_4...
Page 502 EPINFO Data Settings Based on Bluetooth Standard Register Corresponding UEPIRn_0 to UEPI UEPI UEPI UEPI UEPI Name Address Transfer Mode* UEPIRn_4 Settings Rn_0 Rn_1 Rn_2 Rn_3 Rn_3 UEPIR17_0 to H'C00055 Specific to Isoch B'[0011]_01_[01]_[110]_01_0_ H'35 H'C8 H'00 H'00 H'11 UEPIR17_4 to H'C0059 out transfer [0000000000]_0000000000010001*...
Page 503: Usb Control Register (Uctlr)
15.3.2 USB Control Register (UCTLR) UCTLR is used to select USB data input/output pin and USB operating clock, specify SOF marker function, and controls the USB module reset. UCTLR can be read from or written to even in USB module stop mode. For details on UCTLR setting procedure, refer to section 15.5, Communication Operations.
Page 504 Bit Name Initial Value R/W Description UCKS3 USB Operating Clock Selection 0 to 3 UCKS2 Select the USB operating clock (48 MHz). When UCKS0 to UCKS3 are 0000, both the 48-MHz UCKS1 oscillator and internal PLL circuit stop and USB UCKS0 operating clock must be selected according to the clock source.
Page 505 Bit Name Initial Value R/W Description UCKS3 1001: Reserved UCKS2 1010: Reserved UCKS1 1011: Reserved UCKS0 1100: Uses the USB operating clock (48 MHz) directly. The PLL stops. The USB operating clock stabilization time is 8 ms. 1101: Reserved 1110: Reserved 1111: Reserved Note that the USB operating clock stabilization time differs according to the selected clock source and is...
Page 506 Bit Name Initial Value R/W Description UDCRST UDC Core Software Reset Controls reset of the UDC core in the USB module. When the UDCRST bit is set to 1, the UDC core is reset and USB bus synchronization operation stops. At initialization, UDCRST must be cleared to 0 after D+ pull-up following UIFRST clearing to 0.
Page 507: Usb Dmac Transfer Request Register (Udmar)
15.3.3 USB DMAC Transfer Request Register (UDMAR) UDMAR is set when data transfer by means of on-chip DMAC is performed for data registers UEDR2i, UEDR2o, UEDR4i, and UEDR4o corresponding to EP2i, EP2o, EP4i, and EP4o used for Bulk transfer, respectively. DMAC transfer request sources specified in UDMAR must be two or less.
Page 508: Usb Device Resume Register (Udrr)
15.3.4 USB Device Resume Register (UDRR) UDRR indicates remote wakeup according to the host enable/disable state and enables or disables remote wakeup of the USB modules in the suspend state. Bit Name Initial Value R/W Description 7 to 2 — Reserved These bits are always read as 0 and cannot be modified.
Page 509: Usb Trigger Register 0 (Utrg0)
15.3.5 USB Trigger Register 0 (UTRG0) UTRG0 generates one-shot triggers to the FIFO for each endpoint EP0 to EP2. Bit Name Initial Value R/W Description — Reserved — These bits are always read as 0 and cannot be modified. EP2oRDFN 0 EP2o Read Completion 0: Performs no operation 1: Writes 1 to this bit after reading data for EP2o OUT...
Page 510: Usb Trigger Register 1 (Utrg1)
Note: As triggers to EP3i and EP3o for Isochronous transfer are automatically generated each time the SOF packet is received from the host, the user need not generate triggers to EP3i and EP3o. Accordingly, data write to UEDR3i and data read from UEDR3o must be completed before the next packet has been received.
Page 511: Usbfifo Clear Register 0 (Ufclr0)
15.3.7 USBFIFO Clear Register 0 (UFCLR0) UFCLR0 is a one-shot register used to clear the FIFO for each end point from EP0 to EP3. Writing 1 to a bit clears the data in the corresponding FIFO. For IN FIFO, writing 1 to a bit in UFCLR0 clears the data for which the corresponding PKTE bit in UTRG0 is cleared to 0 after data write, or data that is validated by setting the corresponding PKTE bit in UTRG0.
Page 512: Usbfifo Clear Register 1 (Ufclr1)
15.3.8 USBFIFO Clear Register 1 (UFCLR1) UFCLR1 is a one-shot register used to clear the FIFO for each endpoint from EP4 to EP5. Writing 1 to a bit clears the data in the corresponding FIFO. For IN FIFO, writing 1 to a bit in UFCLR1 clears the data for which the corresponding PKTE bit in UTRG1 is cleared to 0 after data write, or data that is validated by setting the corresponding PKTE bit in UTRG1.
Page 513: Usb Endpoint Stall Register 0 (Uestl0)
15.3.9 USB Endpoint Stall Register 0 (UESTL0) UESTL0 is used to forcibly stall the endpoints for EP0 to EP3. While the bit is set to 1, the corresponding endpoint returns a stall handshake to the host. However, note that EP3 (Isochronous transfer) does not return a stall handshake.
Page 514: Usb Endpoint Stall Register 1 (Uestl1)
15.3.10 USB Endpoint Stall Register 1 (UESTL1) UESTL1 is used to forcibly stall the endpoints for EP4 and EP5. In addition, UESTL1 can cancel all endpoint stall states. While the bit is set to 1, the corresponding endpoint returns a stall handshake to the host.
Page 515: Usb Endpoint Data Register 0S (Uedr0S)
15.3.11 USB Endpoint Data Register 0s (UEDR0s) UEDR0s stores the setup command for endpoint 0s (for Control_out transfer). UEDR0s stores 8- byte command data sent from the host in setup stage. For details on USB operation when the data for the next setup stage is received while data in UEDR0s is being read, refer to section 15.9, Usage Notes.
Page 516: Usb Endpoint Data Register 1I (Uedr1I)
15.3.14 USB Endpoint Data Register 1i (UEDR1i) UEDR1i is a data register for endpoint 1i (for Interrupt_in transfer). UEDR1i stores data to be sent to the host. The number of data items to be written continuously must be the maximum packet size or less.
Page 517: Usb Endpoint Data Register 3I (Uedr3I)
15.3.17 USB Endpoint Data Register 3i (UEDR3i) UEDR3i is a data register for endpoint 3i (for Isochronous_in transfer). UEDR3i stores data to be sent to the host. The number of data items to be written continuously must be the maximum packet size or less.
Page 518: Usb Endpoint Data Register 4O (Uedr4O)
15.3.20 USB Endpoint Data Register 4o (UEDR4o) UEDR4o is a data register for endpoint 4o (for Bulk_out transfer). UEDR4o stores data received from the host. The number of data items to be read must be specified by UESZ4o. UEDR4o is a byte register to which 4-byte address area is assigned. Accordingly, UEDR4o allows the user to read 2-byte or 4-byte data by word transfer or longword transfer.
Page 519: Usb Endpoint Receive Data Size Register 2O (Uesz2O)
15.3.23 USB Endpoint Receive Data Size Register 2o (UESZ2o) UESZ2o is the receive data size register for endpoint 2o (for Bulk_out transfer). UESZ2o indicates the number of bytes of data to be received from the host. The FIFO for endpoint 2o (for Bulk_out transfer) has a dual-FIFO configuration. The data size indicated by this register refers to the currently selected FIFO.
Page 520 transmission/reception, and bus reset states. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. A bit in this register can be cleared by writing 0 to it. Writing 1 to a bit is invalid and causes no operation. Bit Name Initial Value R/W Description...
Page 521 Bit Name Initial Value R/W Description EP0iTR R/(W)* EP0i Transfer Request Set to 1 if there is no valid transmit data in the FIFO when an IN token is sent from the host to EP0i. The corresponding interrupt output is EXIRQ0 or EXIRQ1. EP0iTS R/(W)* EP0i Transfer Completion Set to 1 if the transmit data written in EP0i is...
Page 522: Usb Interrupt Flag Register 1 (Uifr1)
15.3.27 USB Interrupt Flag Register 1 (UIFR1) UIFR1 is an interrupt flag register indicating the EP2i, EP2o, EP3i, and EP3o. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested from the CPU. EP2iTR and EP3iTR flags can cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.
Page 523 Bit Name Initial Value R/W Description — Reserved This bit is always read as 0 and cannot be modified. EP2oREADY 0 EP2o Data Ready EP2o FIFO has a dual-FIFO configuration. This flag is set if there is a valid data in at least one EP2o FIFO. This flag is cleared to 0 if there is no valid data in EP2o FIFO.
Page 524: Usb Interrupt Flag Register 2 (Uifr2)
15.3.28 USB Interrupt Flag Register 2 (UIFR2) UIFR2 is an interrupt flag register indicating the state of EP4i, EP4o, and EP5i. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. EP4iTR EP5iTS and EP4iTR flags can cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.
Page 525 Bit Name Initial Value R/W Description EP4iTR R/(W)* EP4i Transfer Request Set to 1 if the EP4i FIFO is empty when an IN token is sent form the host to EPi4. The corresponding interrupt output is EXIRQ0 or EXIRQ1. EP4iEMPTY 1 EP4i FIFO Empty EP4i FIFO has a dual-FIFO configuration.
Page 526: Usb Interrupt Flag Register 3 (Uifr3)
15.3.29 USB Interrupt Flag Register 3 (UIFR3) UIFR3 is an interrupt flag register indicating the USB status. If the corresponding bit is set to 1, the corresponding EXIRQ0, EXIRQ1, or IRQ6 interrupt is requested from the CPU. VBUSi, SPRSi, SETI, SETC, SOF, and CK48READY flags can be cleared by writing 0. Writing 1 to them is invalid and causes no operation.
Page 527 Bit Name Initial Value R/W Description SPRSs Suspend/Resume Status Indicates the suspend/resume status and cannot request an interrupt. 0: Indicates that the bus is in the normal state. 1: Indicates that the bus is in the suspend state. SPRSi R/(W)* Suspend/Resume Interrupt Set to 1 if a transition from normal state to suspend state or suspend state to normal state has occurred.
Page 528: Usb Interrupt Enable Register 0 (Uier0)
15.3.30 USB Interrupt Enable Register 0 (UIER0) UIER0 enables the interrupt request indicated in the interrupt flag register 0 (UIFR0). When an interrupt flag is set while the corresponding bit in UIER0 is set to 1, an interrupt is requested by asserting the corresponding EXIRQ0 or EXIRQ1 pin.
Page 529: Usb Interrupt Enable Register 2 (Uier2)
15.3.32 USB Interrupt Enable Register 2 (UIER2) UIER2 enables the interrupt request indicated in the interrupt flag register 2 (UIFR2). When an interrupt flag is set while the corresponding bit in UIER2 is set to 1, an interrupt is requested by asserting the corresponding EXIRQ0 or EXIRQ1 pin.
Page 530: Usb Interrupt Select Register 0 (Uisr0)
15.3.34 USB Interrupt Select Register 0 (UISR0) UISR0 selects the EXIRQ pin to output interrupt request indicated in the interrupt flag register 0 (UIFR0). When a bit in UIER0 corresponding to the UISR0 bit is set to 1, an interrupt request is output to EXIRQ0.
Page 531: Usb Interrupt Select Register 2 (Uisr2)
15.3.36 USB Interrupt Select Register 2 (UISR2) UISR2 selects the EXIRQ pin to output interrupt request indicated in the interrupt flag register 2 (UIFR2). When a bit in UIER2 corresponding to the UISR2 bit is set to 1, an interrupt request is output to EXIRQ0.
Page 532: Usb Data Status Register (Udsr)
15.3.38 USB Data Status Register (UDSR) UDSR indicates whether the IN FIFO data registers (EP0i, EP1i, EP2i, EP4i, and EP5i) contain valid data or not. A bit in USDR is set when data written to the corresponding IN FIFO becomes valid after the corresponding PKTE bit in UTRG is set to 1.
Page 533: Usb Configuration Value Register (Ucvr)
15.3.39 USB Configuration Value Register (UCVR) UCVR stores the Configuration value, Interface Number value and Alternate Setting value when the Set_Configuration and Set_Interface commands are received from the host. Bit Name Initial Value R/W Description — Reserved — These bits are always read as 0 and cannot be modified.
Page 534: Usb Time Stamp Registers H, L (Utsrh, Utsrl)
15.3.40 USB Time Stamp Registers H, L (UTSRH, UTSRL) UTSRH and UTSRL store the current time stamp values. The time stamp values in UTSRH and UTSRL are modified when the SOF flag in UIFR3 is set to 1. UTSRH combined with UTSRL can also be handled as a 16-bit register. The USB module has an 8-bit bus.
Page 535: Usb Test Register 0 (Utstr0)
15.3.41 USB Test Register 0 (UTSTR0) UTSTR0 controls internal or external transceiver output signals. Setting the PTSTE bit to 1 specifies transceiver output arbitrarily. Table 15.3 shows the relationship between UTSTR0 settings and pin outputs. Bit Name Initial Value R/W Description PTSTE Pin Test Enable...
Page 536: Table 15.3 Relationship Between The Utstr0 Setting And Pin Outputs
Table 15.3 Relationship between the UTSTR0 Setting and Pin Outputs Input Register Setting Pin Outputs UCTLR/ PA3/ P17/ P15/ P13/ FADSEL PTSTE SUSPEND OE VBUS FSE0 VPO USD+ USD- USPND SUSPND FSE0         ...
Page 537: Usb Test Register 1 (Utstr1)
15.3.42 USB Test Register 1 (UTSTR1) UTSTR1 allows internal or external transceiver input signals to be monitored. When the FADSEL bit of UCTLR is set to 0, internal transceiver input signals can be monitored. When the FADSEL bit is FADSEL =1, external transceiver input signals can be monitored. Table 15.4 shows the relationship between UTSTR1 settings and pin inputs.
Page 538: Usb Test Registers 2 And A To F (Utstr2, Utsra To Utsrf)
Table 15.4 Relationship between the UTSTR1 Settings and Pin Inputs Pin Input UTSTR1 Monitor UBPM UBPM UBPM UBPM UBPM UBPM UBPM UBPM VBUS VBUS UTSTR1 Register Settings Pin Input Monitor UCTLR/ UTSTR0/ UTSTR0/ P12/ P11/ P10/ FADSEL PTSTE SUSPEND VBUS USD+ USD- RCV VP VM...
Page 539: Module Stop Control Register B (Mstpcrb)
15.3.44 Module Stop Control Register B (MSTPCRB) Bit Name Initial Value Description 7 to 1 MSTPB7 Module Stop Bits MSTPB6 For details, refer to section 22.1.3, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC). MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Module Stop USB...
Page 540: Interrupt Sources
15.4 Interrupt Sources This module has three interrupt signals. Table 15.5 shows the interrupt sources and their corresponding interrupt request signals. EXIRQ interrupt signals are activated at low level. The EXIRQ interrupt requests can only be detected at low level (specified as level sensitive). The suspend/resume interrupt request IRQ6 must be specified to be detected at the falling edge (falling-edge sensitive) by the interrupt controller register.
Page 541 Interrupt Transfer Interrupt Request DMAC Register Mode Source Description Signal Activation EXIRQ0 or DREQ0 or UIFR2 Bulk_out transfer EP4oREADY EP4o data ready EXIRQ1 DREQ1* (EP4o) — Reserved — — — EXIRQ0 or Interrupt_in transfer EP5iTS EP5i transfer EXIRQ1 (EP5i) completion EXIRQ0 or EP5iTR EP5i transfer request...
Page 542: Communication Operation
15.5 Communication Operation 15.5.1 Initialization The USB must be initialized as described in the flowchart in figure 15.3. USB function Firmware Select USB operating clock (Write UCKS0 to UCKS3 Cancel power-on reset in UCTLR) Cancel USB module stop Start USB operationg clock mode (Clear MSTPB0 in oscillation.
Page 543: Usb Cable Connection/Disconnection
15.5.2 USB Cable Connection/Disconnection (1) USB Cable Connection (when USB module stop or software standby is not used) If the USB cable enters the connection state from the disconnection state in an application (self powered) where USB module stop or software standby mode is not used, perform the operation shown in figure 15.4.
Page 544: Figure 15.5 Usb Cable Connection (When Usb Module Stop Or Software Standby Is Used)
(2) USB Cable Connection (When USB module stop or software standby is used) If the USB cable enters the connection state from disconnection state an application (self powered) where USB module stop or software standby mode is used, perform the operation as shown in figure 15.5.
Page 545: Figure 15.6 Usb Cable Disconnection (When Usb Module Stop Or Software Standby Is Not Used)
(3) USB Cable Disconnection (When USB module stop or software standby is not used) If the USB cable enters the disconnection state from the connection state in an application (self powered) where USB module stop or software standby mode is not used, perform the operation shown in figure 15.6.
Page 546: Figure 15.7 Usb Cable Disconnection (When Usb Module Stop Or Software Standby Is Used)
(4) USB Cable Disconnection (When USB module stop or software standby is used) If the USB cable enters the disconnection state from the connection state in an application (self powered) where USB module stop or software standby mode is used, perform the operation shown in figure 15.7.
Page 547: Suspend And Resume Operations
15.5.3 Suspend and Resume Operations (1) Suspend Operation If the USB bus enters the suspend state from a non-suspend state, perform the operation shown in figure 15.8. USB function Firmware USB cable connected A bus idle of 3 ms or more occurs A suspend/resume interrupt occurs...
Page 548: Figure 15.9 Resume Operation From Up-Stream
(2) Resume Operation from Up-Stream If the USB bus enters a non-suspend state from the suspend state by resume signal output from up-stream, perform the operation shown in figure 15.9. USB function Firmware USB cable connected USB bus in suspend state A resume interrupts in requested from the up-stream.
Page 549: Figure 15.10 Operation When Remote-Wakeup Function Is Used
(3) Resume Operation by the Remote-Wakeup Function If the USB bus enters from suspend state to non-suspend state by the remote-wakeup output from this function, perform the operation as shown in figure 15.10. Firmware USB function USB cable connected Remote wakeup USB bus in suspend state enabled by the host? A bus wakeup source...
Page 550: Control Transfer
15.5.4 Control Transfer The control transfer consists of three stages; setup, data (sometimes omitted), and status, as shown in figure 15.11. The data stage consists of multiple bus transactions. Figures 15.12 to 15.16 show operation flows in each stage. Setup stage Data stage Status stage Control-in...
Page 551: Figure 15.12 Setup Stage Operation
(1) Setup Stage USB function Firmware SETUP token reception Receive 8-byte command data in UEDR0s Command Automatic to be processed by processing by application? this module Clear Setup TS flag Set setup command (UIFR0/Setup TS = 0) reception complete flag Clear EP0i FIFO (UFCLR0/EP0iCLR = 1) (UIFR0/Setup TS = 1) Clear EP0o FIFO (UFCLR0/EP0oCLR = 1)
Page 552 (2) Data Stage (Control-In) The firmware first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (EP0iTS of UIFR0 is set to 1).
Page 553: Figure 15.13 Data Stage Operation (Control-In)
USB function Firmware IN token reception From setup stage Write data to USB endpoint 1 written data register 0i (UEDR0i) to UTRG0/EP0s RDFN? NACK Write 1 to EP0i packet enable bit (UTRG0/EP0i PKTE = 1) Valid data in EP0i FIFO? NACK Data transmission to host Set EP0i transmission...
Page 554: Figure 15.14 Data Stage Operation (Control-Out)
(3) Data Stage (Control-Out) The firmware first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is out-transfer, the application waits for data from the host, and after data is received (EP0oTS of UIFR0 is set to 1), reads data from the FIFO.
Page 555: Figure 15.15 Status Stage Operation (Control-In)
(4) Status Stage (Control-In) The control-in status stage starts with an OUT token from the host. The firmware receives 0- byte data from the host, and ends control transfer. USB function Firmware OUT token reception 0-byte reception from host Set EP0o reception Clear EP0o reception complete flag complete flag...
Page 556: Figure 15.16 Status Stage Operation (Control-Out)
(5) Status Stage (Control-Out) The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer request interrupt is generated.
Page 557: Interrupt-In Transfer: (Ep1I Is Specified As Endpoint)
15.5.5 Interrupt-In Transfer: (EP1i is specified as Endpoint) USB function Firmware Is there data for transmission to host? IN token reception Write data to USB endpoint data register 1i (UEDR1i) Valid data in EP1i FIFO? Write 1 to EP1i packet NACK enable bit (UTRG0/EP1i PKTE = 1)
Page 558: Bulk-In Transfer (Dual Fifos): (Ep2I Is Specified As Endpoint)
15.5.6 Bulk-In Transfer (Dual FIFOs): (EP2i is specified as Endpoint) EP2i has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO.
Page 559: Figure 15.18 Ep2I Bulk-In Transfer Operation
USB function Firmware IN token reception Clear EP2i transfer Valid data request flag in EP2i FIFO? (UIFR1/EP2i TR = 0) NACK Write 1 to EP2i FIFO Data transmission to host empty enable (UIER1/EP2i EMPTYE = 1) Set EP2i Space FIF0 empty status UIFR1/EP2i EMPTY in EP2i FIFO? (UIFR1/EP2i...
Page 560: Bulk-Out Transfer (Dual Fifos): (Ep2O Is Specified As Endpoint)
15.5.7 Bulk-Out Transfer (Dual FIFOs): (EP2o is specified as Endpoint) EP2o has two 64-byte FIFOs, but the user can perform data reception and receive data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the UIFR1/EP2o READY bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately.
Page 561: Figure 15.19 Ep2O Bulk-In Transfer Operation
USB function Firmware OUT token reception Space in EP2o FIFO? NACK Data reception from host Set EP2o Data ready status Read USB endpoint receive data size register 2o (UESZ2o) (UIFR1/EP2o READY = 1) Read data from USB endpoint data register 2o (UEDR2o) Write 1 to EP2o read complete bit (UTRG0/EP2o RDFN = 1)
Page 562: Isochronous-In Transfer (Dual-Fifo) (When Ep3I Is Specified As Endpoint)
15.5.8 Isochronous–In Transfer (Dual-FIFO) (When EP3i is Specified as Endpoint) EP3i has two 128-byte (maximum) FIFOs, however the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. In isochronous transfer, as a transmission is performed once a frame (1 ms), the hardware automatically switches FIFOs when the hardware receives the SOF.
Page 563: Figure 15.20 Ep3I Isochronous-In Transfer Operation
USB function Firmware Clear the SOF packet Receove SOF detection flag (Clear SOF of UIFR3 to 0) EP3i IN token not received Valid data in FIFO B Read USB time stamp (Set EP3i TF of UIFR1 to 1) has been transferred? registers H and L (UTSRH and UTSRL) Switch to FIFO A...
Page 564: Isochronous-Out Transfer (Dual-Fifo) (When Ep3O Is Specified As Endpoint)
15.5.9 Isochronous–Out Transfer (Dual-FIFO) (When EP3o is Specified as Endpoint) EP3o has two 128-byte (maximum) FIFOs, however the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. In isochronous transfer, as a transmission is performed once a frame (1ms), the hardware automatically switches FIFOs when the hardware receives the SOF.
Page 565: Figure 15.21 Ep3O Isochronous-Out Transfer Operation
USB function Firmware Start of Frame Clear the SOF packet Receive SOF detection flag (Clear SOF of UIFR3 to 0) Read USB time stamp Switch to FIFO B-side UIFR1/EP3oTS, EP3oTF update registers H and L (UTSRH and UTSRL) FIFO B FIFO A Receive OUT token Read EP3o statis...
Page 566: 15.5.10 Processing Of Usb Standard Commands And Class/Vendor Commands
15.5.10 Processing of USB Standard Commands and Class/Vendor Commands (1) Processing of Commands Transmitted by Control Transfer A command transmitted from the host by control transfer may require decoding and execution of command processing by the firmware. Whether or not command decoding is required by the firmware is indicated in table 15.6 below.
Page 567 The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application;...
Page 568: Figure 15.22 Forcible Stall By Firmware
(1) Transition from normal operation to stall USB function module (1-1) 1. Set EPnSTL to 1 by Internal status bit EPnSTL firmware 0 → 1 (1-2) Reference 1. Receive IN/OUT Transaction request token from the host EPnSTL Internal status bit 2.
Page 569 (3) Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, when the information of this module differs from that returned to the host by the Get Descriptor, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to EPnSTL, and returns a stall handshake (1-1 in figure 15.23).
Page 570: Figure 15.23 Automatic Stall By Usb Function Module
(1) Transition from normal operation to stall USB function module (1-1) 1. In case of USB specification STALL handshake EPnSTL Internal status bit violation, USB 0 → 1 function module stalls endpoint automatically. To (2-1) or (3-1) (2) When transaction is performed when internal status bit is set (2-1) 1.
Page 571: Dma Transfer Specifications
15.6 DMA Transfer Specifications 15.6.1 Overview This module incorporates the interface that supports dual-address transfer by means of the on-chip DMAC. Endpoints that can be transferred by the on-chip DMAC are EP2 and EP4 in Bulk transfer (corresponding registers are UEDR2i, UEDR2o, UEDR4i, and UEDR4o). In DMA transfer, the USB module must be accessed as an external device in area 6.
Page 572: Ep2Ipkte, Ep4Ipkte, Ep2Ordfn And Ep4Ordfn Bits Of Utrg
15.6.5 EP2iPKTE, EP4iPKTE, EP2oRDFN and EP4oRDFN Bits of UTRG (1) EP2iPKTE and EP4iPKTE When DMA transfer is performed on EP2i and EP4i transmit data, the USB module automatically performs the same processing as writing 1 to EP2iPKTE and EP4iPKTE if one data FIFO (64 bytes) becomes full.
Page 573: Figure 15.25 Ep2Ordfn Operation In Utrg0
(2) EP2oRDFN and EP4oRDFN When DMA transfer is performed on EP2o and EP4o receive data, do not write 1 to EP2oRDFN or EP4oRDFN after one data FIFO (64 bytes) has been read. In data transfer other than DMA transfer, the next data cannot be read after one data FIFO (64 bytes) has been read unless EP2oRDFN and EP4oRDFN are set to 1.
Page 574: Endpoint Configuration Example
15.7 Endpoint Configuration Example Figure 15.26 shows an example of endpoint configuration. EPINFO data for the endpoint configuration shown in figure 15.26 is shown in table 15.8. In this example, two endpoints are not used. However, note that to load all EPINFO data from UEP1R00_0 to UEPIR22_4, dummy data must be written to the unused endpoints.
Page 575: Table 15.7 Register Name Modification List
Table 15.7 Register Name Modification List Register Name Based on Bluetooth Abbrevi- Access Standard Modified Register Name ation Initial Value Address Width UEDR1i USB endpoint data register 3 UEDR3 H'00 H'C0009C (For Interrupt_in data transfer) – H'C0009F UEDR2i USB endpoint data register 2 UEDR2 H'00 H'C000A0...
Page 576: Table 15.8 Bit Name Modification List
Table 15.8 Bit Name Modification List Abbrevi- Initial ation Value Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UDMAR H'00 H'C00082 EP6T1 EP6T0 EP5T1 EP5T0 EP1T1 EP1T0 EP2T1 EP2T0 UTRG0 H'00 H'C00084 –...
Page 577: Table 15.9 Epinfo Data Settings
Table 15.9 EPINFO Data Settings EPINFO Data Settings Based on Bluetooth Standard Register Corresponding UEPIRn_0 to UEPI UEPI UEPI UEPI UEPI Name Address Transfer Mode* UEPIRn_4 Settings* Rn_0 Rn_1 Rn_2 Rn_3 Rn_4 UEPIR00_0 to H'C00000 to Specific to B'0000_00_00_000_00_0_ H'00 H'00 H'40 H'00 H'00 UEPIR00_4 H'C0004 Control transfer...
Page 578 EPINFO Data Settings Based on Bluetooth Standard Register Corresponding UEPIRn_0 to UEPI UEPI UEPI UEPI UEPI Name Address Transfer Mode* UEPIRn_4 Settings* Rn_0 Rn_1 Rn_2 Rn_3 Rn_4 UEPIR18_0 to H'C0005A to Specific to Isoch B'[0000]_01_[00]_[000]_01_1_ H'04 H'0C H'00 H'00 H'12 UEPIR18_4 H'C005E in transfer...
Page 579: Usb External Circuit Example
15.8 USB External Circuit Example Figures 15.27 and 15.28 show the USB external circuit examples when the on-chip transceiver is used. Figures 15.29 and 15.30 show the USB external circuit examples when an external transceiver is used. Internal transceiver DrVCC USD+ USD- DrVSS...
Page 580: Figure 15.28 Usb External Circuit In Self-Powered Mode (When On-Chip Transceiver Is Used)
Internal transceiver DrVCC VBUS (3.3V) USD+ USD- DrVSS (3.3V) (P36) 1: Self-powered mode 1.5k Pull-up control external circuit VBUS for full speed (5V) USB connector Notes: Notes:* To protect the LSI, voltage applicable IC such as HD74LV-A series must be used even when the system power is turned off.
Page 581: Figure 15.29 Usb External Circuit In Bus-Powered Mode (When External Transceiver Is Used)
DrVCC VBUS (3.3V) DrVSS (P36) (3.3V) External transceiver (PDIUSBP11A manufactured by Phillips Corp. ) (3.3V) 0: Bus-powered mode Regulator VBUS 1.5k (5V) Pull-up control external circuit USB connector for full speed Notes: Notes: Notes:* Step-down to the operating voltage VCC(3.3V) of this LSI. To protect the LSI, voltage applicable IC such as HD74LV-A series must be used even when the system power is turned off.
Page 582: Figure 15.30 Usb External Circuit In Self-Powered Mode (When External Transceiver Is Used)
DrVCC (P36) (3.3V) VBUS (3.3V) DrVSS External transceiver (PDIUSBP11A manufactured by Phillips Corp. ) 1: Self-powered mode 1.5k Pull-up control external circuit VBUS for full speed (5V) USB connector Notes: Notes:* To protect the LSI, voltage applicable IC such as HD74LV-A series must be used even when the system power is turned off.
Page 583: Usage Notes
15.9 Usage Notes 15.9.1 Operating Frequency When the on-chip PLL circuit is used, the system clock of this LSI must be 16 MHz. This 16-MHz system clock, used as base clock, is tripled in the on-chip PLL circuit to generate the 48-MHz USB operating clock.
Page 584: Data Register Overread Or Overwrite
15.9.6 Data Register Overread or Overwrite When the CPU reads or writes to data registers, the following must be noted: • Transmit data registers (UEDR0i, UEDR1i, UEDR2i, UEDR3i, UEDR4i, UEDR5i) Data to be written to the transmit data registers must be within the maximum packet size. For the transmit data registers of EP2i, EP3i, and EP4i having a dual-FIFO configuration, data to be written at any time must be within the maximum packet size.
Page 585: Ep3O Isochronous Transfer
15.9.7 EP3o Isochronous Transfer • Reception of EP3o data larger than the maximum packet size The EP3o data FIFO cannot receive data with size larger than the maximum packet size; the excessive data is lost. In this case, the receive size register (UESZ3o) can count up to the maximum packet size and the EP3o abnormal transfer flag (EP3oTF) is set to 1.
Page 586: Figure 15.32 Ep3O Data Reception
[In frame N] Internal flag (A-side) UIFR1 EP3o FIFO A Data (1) Modify No change Receive USB — — data (1) Internal flag (B-side) EP3o FIFO B — — — Next frame [In frame N+1] EP3o FIFO A Internal flag (A-side) UIFR1 Data (1) A-side flag update...
Page 587: Reset
15.9.8 Reset A manual reset should not be performed during USB communication as the LSI will stop with the USD+, USD- pin state maintained. This USB module uses synchronous reset for some registers. The reset state of these registers must be cancelled after the clock oscillation stabilization time has passed.
Page 588: 15.9.12 Restrictions For Software Standby Mode Transition
transfer instructions. To write 7-byte data correctly, data must be written once by a longword transfer instruction, once by a word transfer instruction, and once by a byte transfer instruction, or data must be written three times by a word transfer instruction and once by a byte transfer instruction.
Page 589: Figure 15.33 Transition To And From Software Standby Mode
Procedure to enter software standby mode Procedure to cancel software standby mode Specify to falling edge sensitive Detect USB bus resume (10) (Set IRQ6E of IER to 1) USPND pin = Low (Write IRQ6SCB and A of ISCRH to 01) (11) = Low (falling edge output) Set IRQ6F of ISR to 1...
Page 590: 15.9.13 Usb External Circuit Example
(10) (24) USB bus state Normal Suspend Resume Normal USPND (10) (11) (23) (15) ISR/IRQ6F (11) UIFR3/SPRSi (22) (19) (19) UIFR3/SPRSs UIFR3/SOF (25) UCTLR/SFME (26) USB module (16) stop Standby mode (12) System clock (16 MHz) (13) (16 MHz) (14) USB internal clock (17) (16 MHz)
Page 591: Section 16 A/D Converter
Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to six analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1. 16.1 Features • 10-bit resolution •...
Page 592: Figure 16.1 Block Diagram Of A/D Converter
Module data bus Internal data bus AVCC Vref 10 bit D/A AVSS Comparator Control circuit AN14 Sample and hold circuit AN15 ADI interrupt signal Time conversion start trigger from TPU or 8 bit timer Legend: ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B...
Page 593: Input/Output Pins
16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The AN0 to AN3 and AN14 to AN15 pins are analog input pins. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the reference voltage pin for the A/D conversion.
Page 594: A/D Control/Status Register (Adcsr)
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register.
Page 595 Bit Name Initial Value Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends • When A/D conversion ends on all specified channels [Clearing conditions] • When 0 is written after reading ADF = 1 •...
Page 596: A/D Control Register (Adcr)
16.3.3 A/D Control Register (ADCR) The ADCR enables A/D conversion started by an external trigger signal. Bit Name Initial Value Description TRGS1 Timer Trigger Select 0 and 1 TRGS0 Enables the start of A/D conversion by a trigger signal. Only set bits TRGS0 and TRGS1 while conversion is stopped (ADST = 0).
Page 597: Interface To Bus Master
16.4 Interface to Bus Master ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus master accesses to the upper byte of the registers directly while to the lower byte of the registers via the temporary register (TEMP).
Page 598: Operation
16.5 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed.
Page 599: Scan Mode
Set* ADIE Set* Set* conversion starts ADST Clear* Clear* State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle Idle Idle A/D conversion A/D conversion State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle ADDRA Read conversion result Read conversion result ADDRB...
Page 600: Input Sampling And A/D Conversion Time
Continuous A/D conversion execution Clear* Set* ADST Clear* A/D conversion time State of channel 0 (AN0) Idle Idle Idle A/D conversion 4 A/D conversion 1 State of channel 1 (AN1) Idle Idle Idle A/D conversion 2 A/D conversion 5 State of channel 2 (AN2) Idle Idle A/D conversion 3...
Page 601: Figure 16.5 A/D Conversion Timing
ø Address Write signal Input sampling timing CONV Legend : ADCSR write cycle : ADCSR address : A/D conversion start delay : Input sampling time : A/D conversion time CONV Figure 16.5 A/D Conversion Timing Table 16.3 A/D Conversion Time (Single Mode) Item Symbol CKS1 = 0...
Page 602: External Trigger Input Timing
16.5.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Page 603: A/D Conversion Precision Definitions
16.7 A/D Conversion Precision Definitions This LSI's A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.7). •...
Page 604: Figure 16.7 A/D Conversion Precision Definitions (1)
Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 16.7 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 16.8 A/D Conversion Precision Definitions (2) Rev.
Page 605: Usage Notes
16.8 Usage Notes 16.8.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 606: Notes On Board Design
• Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. • Vref input range The analog reference voltage input at the Vref pin set is the range Vref ≤...
Page 607: Figure 16.10 Example Of Analog Input Protection Circuit
AVCC Vref AN0 to AN11 0.1 F AVSS Notes: Values are reference values. 10 F 0.01 F *2 R : Input impedance Figure 16.10 Example of Analog Input Protection Circuit Table 16.6 Analog Pin Specifications Item Unit Analog input capacitance — Permissible signal source —...
Page 608 Rev. 3.0, 10/02, page 550 of 686...
Page 609: Section 17 D/A Converter
Section 17 D/A Converter 17.1 Features D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode •...
Page 610: Input/Output Pins
17.2 Input/Output Pins Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration Pin Name Symbol Function Analog power pin AVCC Input Analog power Analog ground pin AVSS Input Analog ground and reference voltage Analog output pin 0 Output Channel 0 analog output...
Page 611: D/A Control Register (Dacr)
17.3.2 D/A Control Register (DACR) DACR controls the operation of the D/A converter. DACR01 Bit Name Initial Value Description DAOE1 D/A Output Enable 1 DAOE0 D/A Output Enable 0 D/A Enable Control the D/A conversion and analog output. 00x: Channel 0 and 1 D/A conversions disabled 010: Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 011: Channel 0 and 1 D/A conversions enabled...
Page 612: Figure 17.2 Example Of D/A Converter Operation
[2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started. The conversion result is output after the conversion time t has elapsed. The output value is expressed by the following DCONV formula: DADR contents ——————— × Vref The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0.
Page 613: Section 18 Ram
Section 18 RAM This LSI has 16 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer.
Page 614 Rev. 3.0, 10/02, page 556 of 686...
Page 615: Section 19 Flash Memory (F-Ztat Version)
Features • Size Product Category ROM Size ROM Addresses H'000000 to H'03FFFF H8S/2215 Series HD64F2215,HD64F2215U 256 kbytes (Modes 6 and 7) • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 616: Figure 19.1 Block Diagram Of Flash Memory
Internal address bus (upper 8 bits) Internal data bus (lower 8 bits) FLMCR1 FWE pin FLMCR2 Bus interface/controller Operating Mode pins EBR1 mode (MD2 to MD0) PF3, PF0, P16, P14 EBR2 RAMER H'000000 H'000001 H'000002 H'000003 Flash memory (256 kbytes) H'03FFFE H'03FFFF Legend...
Page 617: Mode Transitions
19.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not programmed or erased.
Page 618: Table 19.1 Differences Between Boot Mode And User Program Mode
Table 19.1 Differences between Boot Mode and User Program Mode SCI,USB Boot Mode User Program Mode User Mode Total erase Block erase Programming control Program/program-verify Erase/erase-verify — program* Program/program-verify Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev.
Page 619: Figure 19.3 Boot Mode
1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the this LSI (originally incorporated in the chip) is programming control program and new started and the programming control program in application program beforehand in the host.
Page 620: Figure 19.4 User Program Mode
1. Initial state 2. Programming/erase control program transfer The FWE assessment program that confirms that When user program mode is entered, user user program mode has been entered, and the software confirms this fact, executes transfer program that will transfer the programming/erase program in the flash memory, and transfers the control program from flash memory to on-chip programming/erase control program to RAM.
Page 621: Block Configuration
19.3 Block Configuration Figure 19.5 shows the block configuration of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 4 kbytes (eight blocks), 32 kbytes (one block), and 64 kbytes (three blocks).
Page 622: Input/Output Pins
19.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 19.2. Table 19.2 Pin Configuration Pin Name Function Input Reset HD64F2215 Input Flash program/erase protection by hardware HD64F2215U MD2,MD1,MD0 Input Sets this LSI’s operating mode PF3,PF0,P16, Input Sets this LSI’s operating mode in...
Page 623: Flash Memory Control Register 1 (Flmcr1)
19.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.8, Flash Memory Programming/Erasing. Bit Name Initial Value Description —* Reflects the input level at the FWE pin.
Page 624: Flash Memory Control Register 2 (Flmcr2)
Bit Name Initial Value Description Program-Verify: When this bit is set to 1, the flash memory transits to program-verify mode. When it is cleared to 0, program- verify mode is cancelled. [Setting condition] When FWE=1 and SWE1=1 Erase: When this bit is set to 1 while the SWE1 and ESU1 bits are 1, the flash memory transits to erase mode.
Page 625: Erase Block Register 1 (Ebr1)
19.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H’00 when the SWE bit in FLMCR is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Page 626: Erase Block Register 2 (Ebr2)
19.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR2 is initialized to H’00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Page 627: Ram Emulation Register (Ramer)
19.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified.
Page 628: Serial Control Register X (Scrx)
19.5.6 Serial Control Register X (SCRX) SCRX performs register access control. Bit Name Initial Value Description 7 to 4 — Reserved: The write value should always be 0. FLSHE Flash Memory Control Register Enable: Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2).
Page 629: On-Board Programming Modes
19.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode.
Page 630: Figure 19.6 Sci System Configuration In Boot Mode
H8S/2215 Series FWE* MD2 to 0* Flash memory Host Write data reception RxD2 SCI_2 On-chip RAM Verify data transmission TxD2 Note: * FWE pin and mode pin input must satisfy the mode programming setup time (t = 200 ns) when a reset is released.
Page 631 5. In boot mode, a part of the on-chip RAM area (4 kbytes) is used by the boot program. Addresses H’FFE000 to H’FFEFBF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program.
Page 632: Table 19.4 Sci Boot Mode Operation
Table 19.4 SCI Boot Mode Operation Item Host Operation LSI Operation Branches to boot program at reset-start. Bit rate adjustment Continuously transmits data H'00 Measures low-level period of at specified bit rate. receive data H'00. Calculates bit rate and sets it in BRR of SCI_2.
Page 633: Usb Boot Mode (Hd64F2215U)
19.6.2 USB Boot Mode (HD64F2215U) • Features - Selection of bus power mode or self power mode - Supports only 16 MHz system clock, with USB operating clock generation by means of PLL3 multiplication - D+ pull-up control connection supported for P36 pin only - See table 19.6 for enumeration information Table 19.6 Enumeration Information USB standard...
Page 634: Figure 19.7 System Configuration Diagram When Using Usb Boot Mode
(flash memory programming is performed). Figure 19.7 shows a system configuration diagram when using USB boot mode. H8S/2215 Series FWE* EXTAL System clock: 16 MHz MD2-0* XTAL EXTAL48 Open XTAL48 Flash memory Host or self-powered HUB Ω...
Page 635 programming control program and the host. The contents of CPU general registers are undefined after a branch to the programming control program. Note, in particular, that since the stack pointer is used implicitly in subroutine calls and the like, it should be initialized at the start of the programming control program.
Page 636: Table 19.7 Usb Boot Mode Operation
Table 19.7 USB Boot Mode Operation Item Host Operation Operation of this LSI Branches to boot program after reset start Start of USB boot mode Transmits one H'55 byte on completion of USB enumeration Transmits one H'AA byte to host on reception of H'55 Transfer clock information Transmits frequency (2 bytes), number of multiplication...
Page 637 Item Host Operation Operation of this LSI Memory erasure If erasure cannot be performed when total erase If H'11 is received, retransmits total status command is received, erase status command (H'3A) transmits H'EE to host and halts operation Execution of programming Branches to programming control program control program transferred...
Page 638: Figure 19.8 Programming/Erasing Flowchart Example In User Program Mode
19.6.3 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
Page 639: Programming/Erasing In User Program Mode
19.7 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 640: Flash Memory Emulation In Ram
3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P1 or E1 bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode.
Page 641: Flash Memory Programming/Erasing
19.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Page 642: Figure 19.11 Program/Program-Verify Flowchart
Start of programming Write pulse application subroutine Perform programming in the erased state. START Subroutine Write Pulse Do not perform additional programming on previously programmed addresses. Set SWE1 bit in FLMCR1 WDT enable Wait (x) µs Set PSU1 bit in FLMCR1 Store 128-byte program data in program data area and reprogram data area Wait (y) µs...
Page 643: Erase/Erase-Verify
19.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.12 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1).
Page 644: Figure 19.12 Erase/Erase-Verify Flowchart
Start Set SWE1 bit in FLMCR1 Wait (x) µs n = 1 Set EBR1 (2) Enable WDT Set ESU1 bit in FLMCR1 Wait (y) µs Set E1 bit in FLMCR1 Wait (z) µs Clear E1 bit in FLMCR1 Wait ( ) µs Clear ESU1 bit in FLMCR1 Wait ( ) µs Disable WDT...
Page 645: Program/Erase Protection
19.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized.
Page 646: Interrupt Handling When Programming/Erasing Flash Memory
In programmer mode, a PROM programmer can perform programming/erasing via a socket adapter, just like for a discrete flash memory. Use a PROM programmer which supports the Hitachi 256-kbyte flash memory on-chip MCU device type. Memory map in programmer mode is shown in figure 19.13.
Page 647: Power-Down States For Flash Memory
(1) Use the specified voltages and timing for programming and erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Hitachi microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A).
Page 648 (3) FWE application/disconnection FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: •...
Page 649: Note On Switching From F-Ztat Version To Masked Rom Version
In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. (9) Before programming, check that the chip is correctly mounted in the PROM programmer Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned.
Page 650 Rev. 3.0, 10/02, page 592 of 686...
Page 651: Section 20 Masked Rom
This LSI incorporates a masked ROM which has the following features. 20.1 Features • Size: Product Class ROM Size ROM Address (Modes 6 and 7) H8S/2215 series HD6432215A 256 kbytes H’000000 to H’03FFFF HD6432215B 128 kbytes H’000000 to H’01FFFF HD6432215C 64 kbytes H’000000 to H’00FFFF...
Page 652 Rev. 3.0, 10/02, page 594 of 686...
Page 653: Section 21 Clock Pulse Generator
Section 21 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, duty adjustment circuit, medium-speed clock divider, bus master clock selection circuit, USB operating clock oscillator, PLL (Phase Locked Loop) circuit, and USB operating clock selection circuit.
Page 654: Register Descriptions
21.1 Register Descriptions The on-chip clock pulse generator has the following registers. • System clock control register (SCKCR) • Low-power control register (LPWRCR) 21.1.1 System Clock Control Register (SCKCR) SCKCR controls ø clock output and medium-speed mode. Rev. 3.0, 10/02, page 596 of 686...
Page 655 Bit Name Initial Value R/W Description PSTOP ø Clock Output Disable: Controls ø output. High-speed Mode, Medium-Speed Mode 0: ø output 1: Fixed high Sleep Mode 0: ø output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance...
Page 656: Low-Power Control Register (Lpwrcr)
21.1.2 Low-Power Control Register (LPWRCR) Bit Name Initial Value R/W Description 7 to — These bits can be read from or written to, but the write value should always be 0. RFCUT Built-in Feedback Resistor Control: Selects whether the oscillator’s built-in feedback resistor and duty adjustment circuit are used with external clock input.
Page 657: System Clock Oscillator
21.2 System Clock Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 20 MHz. 21.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 21.2. Select the damping resistance Rd according to table 21.2.
Page 658: Inputting An External Clock
21.2.2 Inputting an External Clock An external clock signal can be input as shown in an example in figure 21.4. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. When complementary clock input to XTAL pin, the external clock input should be fixed high in standby mode.
Page 659: Duty Adjustment Circuit
EXTAL Figure 21.5 External Clock Input Timing The external clock input conditions when the duty adjustment circuit is not used are shown in table 21.4. When the duty adjustment circuit is not used, note that the maximum operating frequency depends on the external clock input waveform. For example, if t = 31.25ns and t = 6.25 ns, the maximum operating frequency becomes 13.3 MHz depending on the clcok cycle time of 75 ns.
Page 660: Usb Operating Clock
Since the frequency for USB requires high accuracy, the official product type name will be defined after the performance of the user's board on which the resonator is mounted is evaluated and its fre- quency is adjusted. Please contact your Hitachi sales agency. Figure 21.6 Connection of Ceramic Resonator 21.6.2 Inputting an 48-MHz External Clock An external clock signal can be input as shown in an example in figure 21.7.
Page 661: Pin Handling When 48-Mhz External Clock Is Not Needed
Table 21.5 External Clock Input Conditions when Duty Adjustment Circuit is not Used Item Symbol Unit Test Conditions External clock frequency 47.88 48.12 Figure 21.8 FREQ (48 MHz) Clock rise time — Clock fall time — Duty (t HIGH FREQ DUTY FREQ HIGH...
Page 662: Usage Notes
PLLVCC PLLVCC 13- to 16-MHz EXTAL EXTAL R1: 3k C1: 470pF 16-MHz crystal crystal Open state PLLCAP PLLCAP resonator resonator or external or external CPB: 0.1 F* XTAL XTAL clock clock PLLVSS PLLVSS EXTAL48 EXTAL48 48-MHz crystal resonator or external CB: 0.1 F* XTAL48 XTAL48...
Page 663: Note On Switchover Of External Clock
Signal A Signal B Prohibit H8S/2215 Series XTAL or XTAL48 EXTAL or EXTAL48 Figure 21.11 Note on Board Design of Oscillator Circuit 21.8.3 Note on Switchover of External Clock When two or more external clocks (e.g. 16 MHz and 13 MHz) are used as the system clock, switchover of the input clock should be carried out in software standby mode.
Page 664: Figure 21.13 Example Of External Clock Switchover Timing
External clock 1 External clock 2 Clock switchover SLEEP instruction Interrupt exception handling Operation request execution Port setting External clock switchover signal EXTAL Internal clock ø Wait time External 200 ns or more interrupt Active (external clock 2) Software standby mode Active (external clock 1) Port setting (clock switchover) Software standby mode transition...
Page 665: Section 22 Power-Down Modes
Section 22 Power-Down Modes In addition to the normal program execution state, this LSI has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
Page 666: Table 22.1 Lsi Internal States In Each Mode
Table 22.1 LSI Internal States in Each Mode Medium- Module Software Hardware Function High-Speed Speed Sleep Stop Standby Standby System clock pulse Functioning Functioning Functioning Functioning Halted Halted generator Instructions Functioning Medium- Halted High/ Halted Halted speed medium- (retained) (undefined) Registers (retained) operation...
Page 667: Figure 22.1 Mode Transition Diagram
Program-halted state Reset Execution state pin = Low Manual Hardware reset Reset state standby mode pin = High state pin = Low pin = High SSBY = 0 Program execution state Sleep mode SLEEP command (main clock) High-speed mode (main clock) Any interrupt SLEEP SCK2 to...
Page 668: Register Descriptions
22.1 Register Descriptions The registers relating to the power down mode are shown below. • Standby control register (SBYCR) • System clock control register (SCKCR) • Module stop control register A (MSTPCRA) • Module stop control register B (MSTPCRB) • Module stop control register C (MSTPCRC) 22.1.1 Standby Control Register (SBYCR) SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Page 669 Bit Name Initial Value Description SSBY Software Standby: This bit specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode when the SLEEP instruction is executed 1: Shifts to software standby mode when the SLEEP instruction is executed This bit does not change when clearing software standby mode by using external interrupts and shifting to normal operation.
Page 670: System Clock Control Register (Sckcr)
22.1.2 System Clock Control Register (SCKCR) SCKCR performs ø clock output control and medium-speed mode control. Bit Name Initial Value Description PSTOP ø Clock Output Disable This bit controls ø output. 0: Outputs ø clock in normal operating state and sleep mode.
Page 671 MSTPCRA Bit Name Initial Value Module MSTPA7 DMA controller (DMAC) MSTPA6 Data transfer controller (DTC) MSTPA5 16-bit timer pulse unit (TPU) MSTPA4 8-bit timer (TMR_0, TMR_1) MSTPA3* — MSTPA2* — MSTPA1 A/D converter MSTPA0* — MSTPCRB Bit Name Initial Value Module MSTPB7 Serial communication interface 0 (SCI_0)
Page 672: Medium-Speed Mode
22.2 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium- speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC or DMAC) also operate in medium-speed mode.
Page 673: Sleep Mode
22.3 Sleep Mode 22.3.1 Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained.
Page 674: Clearing Software Standby Mode
22.4.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, IRQ7 pin, or IRQ0 to IRQ5 pins), or by means of the RES pin, MRES pin, or STBY pin. • Clearing with an interrupt When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started.
Page 675: Software Standby Mode Application Example
Table 22.3 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time MHz Unit 8192 states 0.51 0.6 16384 states 32768 states 16.4 65536 states 10.9 16.4 32.8 131072 states 10.1 13.1 16.4 21.8 32.8 65.5 262144 states 16.4 20.2 26.2 32.8 43.6 65.6 131.2 2048 states 0.13 0.16 0.2 16 states...
Page 676: Hardware Standby Mode
Oscillator NMIEG SSBY NMI exception Software standby mode NMI exception handling (power-down mode) handling NMIEG = 1 SSBY = 1 Oscillation SLEEP instruction stabilization time t OSC2 Figure 22.3 Software Standby Mode Application Example 22.5 Hardware Standby Mode 22.5.1 Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
Page 677: Hardware Standby Mode Timing
driven high, a transition is made to the program execution state via the reset exception handling state. 22.5.3 Hardware Standby Mode Timing Figure 22.4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode.
Page 678: Module Stop Mode
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained RES does not have to be driven low as in the above case. Timing of Recovery from Hardware Standby Mode Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a power-on reset.
Page 679: Usage Notes
for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set. Table 22.4 shows the state of the ø pin in each processing state. Table 22.4 ø Pin State in Each Processing State Register Settings Software Hardware...
Page 680 Rev. 3.0, 10/02, page 622 of 686...
Page 681: Section 23 List Of Registers
Section 23 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) •...
Page 682 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module USB end point information register UEPIR00_0 to H'C00000 to 00_0 to 22_4 UEPIR22_4 H'C00072 USB control register UCTLR H'C00080 USB test register A UTSTRA H'C00081 USB DMAC transfer request register UDMAR H'C00082...
Page 683 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module USB endpoint data register 4i UEDR4i H'C000B0 to H'C000B3 USB endpoint data register 4o UEDR4o H'C000B4 to H'C000B7 USB endpoint data register 5i UEDR5i H'C000B8 to H'C000BB USB endpoint receive data size register 0o UESZ0o H'C000BC...
Page 684 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module DTC mode register A H'EBC0 16/32 DTC source address register 16/32 DTC mode register B H’EFBF 16/32 DTC destination address register 16/32 DTC transfer count register A 16/32 DTC transfer count register B 16/32...
Page 685 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module Port A data direction register PADDR H'FE39 PORT Port B data direction register PBDDR H'FE3A Port C data direction register PCDDR H'FE3B Port D data direction register PDDDR H'FE3C Port E data direction register...
Page 686 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module Memory address register 0A H MAR0AH H'FEE0 DMAC Memory address register 0A L MAR0AL H'FEE2 I/O address register 0A IOAR0A H'FEE4 Transfer count register 0A ETCR0A H'FEE6 Memory address register 0B H...
Page 687 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module Timer general register B_0 TGRB_0 H'FF1A TPU_0 Timer general register C_0 TGRC_0 H'FF1C Timer general register D_0 TGRD_0 H'FF1E Timer control register_1 TCR_1 H'FF20 TPU_1 Timer mode register_1 TMDR_1 H'FF21...
Page 688 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module Time constant register B1 TCORB_1 H'FF6F TMR_1 Timer counter_0 TCNT_0 H'FF70 TMR_0 Timer counter_1 TCNT_1 H'FF71 TMR_1 Timer control/status register TCSR H'FF74 Timer counter TCNT H'FF74 (write) Timer counter...
Page 689 Number Number Data Bus Of Access Register Name Abbreviation of Bits Address Width States Module A/D data register AL ADDRAL H'FF91 A/D data register BH ADDRBH H'FF92 A/D data register BL ADDRBL H'FF93 A/D data register CH ADDRCH H'FF94 A/D data register CL ADDRCL H'FF95 A/D data register DH...
Page 690: Register Bits
23.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 16-bit registers are shown as two lines and 32-bit registers as four lines. Rev. 3.0, 10/02, page 632 of 686...
Page 691 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module UEPIRnn_0* UEPIRnn_1* UEPIRnn_2* UEPIRnn_3* UEPIRnn_4* UCTLR FADSEL SFME UCKS3 UCKS2 UCKS1 UCKS0 UIFRST UDCRST        ...
Page 692 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module    UIFR2 EP5iTR EP5iTS EP4oREADY EP4iTR EP4iEMPTY USB UIFR3 CK48 SETC SETI SPRSs SPRSi VBUSs VBUSi READY  UIER0 BRSTE EP1iTRE EP1iTSE...
Page 693 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module                      ...
Page 694 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module    P7DDR P74DDR P73DDR P72DDR P71DDR P70DDR PORT     PADDR PA3DDR PA2DDR PA1DDR PA0DDR PBDDR PB7DDR PB6DDR PB5DDR PB4DDR...
Page 695 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module    BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0       BCRL BRLE WAITE    ...
Page 696 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IOAR1B Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DMAC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 697 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1     TMDR_1 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0...
Page 698 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module     DMABCR* FAE1 FAE0 DTA1 DTA0 DMAC DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0...
Page 699 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BRR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCI_2 SCR_2 MPIE TEIE CKE1 CKE0 TDR_2...
Page 700: Register States In Each Operating Mode
23.3 Register States in Each Operating Mode Register Power-on Manual High- Medium- Sleep Module Software Hardware Module Name Reset Reset Speed Speed Stop Standby Standby         UEPIR00_0 to UEPIR22_4     ...
Page 701 Register Power-on Manual High- Medium- Sleep Module Software Hardware Module Name Reset Reset Speed Speed Stop Standby Standby       UIER1 Initialized Initialized       UIER2 Initialized Initialized     ...
Page 702 Register Power-on Manual High- Medium- Sleep Module Software Hardware Module Name Reset Reset Speed Speed Stop Standby Standby      MSTPCRB Initialized Initialized Initialized SYSTEM      MSTPCRC Initialized Initialized Initialized    ...
Page 703 Register Power-on Manual High- Medium- Sleep Module Software Hardware Module Name Reset Reset Speed Speed Stop Standby Standby      TSTR Initialized Initialized Initialized      TSYR Initialized Initialized Initialized     ...
Page 704 Register Power-on Manual High- Medium- Sleep Module Software Hardware Module Name Reset Reset Speed Speed Stop Standby Standby       P7DR Initialized Initialized PORT       PADR Initialized Initialized    ...
Page 705 Register Power-on Manual High- Medium- Sleep Module Software Hardware Module Name Reset Reset Speed Speed Stop Standby Standby      TGRB_2 Initialized Initialized Initialized TPU_2      DMAWER Initialized Initialized Initialized DMAC   ...
Page 706 Register Power-on Manual High- Medium- Sleep Module Software Hardware Module Name Reset Reset Speed Speed Stop Standby Standby    RDR_1 Initialized Initialized Initialized Initialized Initialized SCI_1      SCMR_1 Initialized Initialized Initialized    ...
Page 707: Section 24 Electrical Characteristics
Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.3 V , PLLV , Input voltage (except ports 4 and 9) V –0.3 to V +0.3 Input voltage (ports 4 and 9)
Page 708: Power Supply Voltage And Operating Frequency Range
24.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24.1. (1) When on-chip USB is not used f(MHz) system clock 16.0 13.0 Vcc, PLLVcc, DrVcc, AVcc (V) (2) When on-chip USB is used system clock f(MHz) 16.0...
Page 709: Dc Characteristics
24.3 DC Characteristics Table 24.2 lists the DC characteristics. Table 24.3 lists the permissible output currents. Table 24.2 DC Characteristics Conditions: V = PLL V =Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV = PLLAV Dr V = 0 V, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range...
Page 710 Test Item Symbol Unit Conditions RES, STBY, Input leakage — — µA = 0.5 V to NMI, MD2 to – 0.5 V current MD0, FWE* VBUS,UBPM Ports 4, 9 — — µA V = 0.5 V to – 0.5 V Current Normal —...
Page 711 Notes:* 1 If the A/D or D/A converter is not used, the AVCC, V , and AVSS pins should not be open. Even if the A/D or D/A converter is not used, connect the AVCC and V pins to and the AVSS pin to V , respectively.
Page 712: Ac Characteristics
Table 24.3 Permissible Output Currents Conditions: V = PLL V =Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV = PLLAV Dr V = 0 V, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications*) Item Symbol Min...
Page 713: Clock Timing
24.4.1 Clock Timing Table 24.4 lists the clock timing Table 24.4 Clock Timing Conditions: V = PLL V =Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV = PLLAV = 0 V, φ =13 MHz to 16 MHz, Dr V = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range...
Page 714: Control Signal Timing
EXTAL DEXT DEXT OSC1 OSC1 φ Figure 24.4 Oscillation Stabilization Timing 24.4.2 Control Signal Timing Table 24.5 lists the control signal timing. Table 24.5 Control Signal Timing Conditions: V = PLL V =Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV = PLLAV = 0 V, φ...
Page 715: Figure 24.5 Reset Input Timing
ø RESS RESS MRESS MRESS RESW MRESW Figure 24.5 Reset Input Timing NMIS NMIH NMIW IRQW IRQS IRQH edge input IRQS level input Figure 24.6 Interrupt Input Timing Rev. 3.0, 10/02, page 657 of 686...
Page 716: Bus Timing
24.4.3 Bus Timing Table 24.6 shows, Bus Timing. Table 24.6 Bus Timing Conditions: V = PLL V =Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV = PLLAV = 0 V, φ =13 MHz to 16 MHz, Dr V = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 717: Figure 24.7 Basic Bus Timing (Two-State Access)
ø A23 to A0 RSD2 RSD1 ACC2 (read) ACC3 D15 to D0 (read) WRD2 WRD2 (write) WSW1 D15 to D0 (write) Figure 24.7 Basic Bus Timing (Two-State Access) Rev. 3.0, 10/02, page 659 of 686...
Page 718: Figure 24.8 Basic Bus Timing (Three-State Access)
ø A23 to A0 RSD1 ACC4 RSD2 (read) ACC5 D15 to D0 (read) WRD1 WRD2 (write) WSW2 D15 to D0 (write) Figure 24.8 Basic Bus Timing (Three-State Access) Rev. 3.0, 10/02, page 660 of 686...
Page 719: Figure 24.9 Basic Bus Timing (Three-State Access With One Wait State)
ø A23 to A0 (read) D15 to D0 (read) (write) D15 to D0 (write) Figure 24.9 Basic Bus Timing (Three-State Access with One Wait State) Rev. 3.0, 10/02, page 661 of 686...
Page 720: Figure 24.10 Burst Rom Access Timing (Two-State Access)
T2 or T3 ø A23 to A0 RSD2 (read) ACC3 D15 to D0 (read) Figure 24.10 Burst ROM Access Timing (Two-State Access) Rev. 3.0, 10/02, page 662 of 686...
Page 721: Figure 24.11 External Bus Release Timing
ø BRQS BRQS BACD BACD A23 to A0, Figure 24.11 External Bus Release Timing Rev. 3.0, 10/02, page 663 of 686...
Page 722: Timing Of On-Chip Supporting Modules
24.4.4 Timing of On-Chip Supporting Modules Table 24.7 lists the timing of on-chip supporting modules. Table 24.7 Timing of On-Chip Supporting Modules Conditions: V = PLL V =Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV = PLLAV = 0 V, φ...
Page 723 Item Symbol Unit Test Conditions Input Asynchro- — Figure 24.18 Scyc clock nous cycle Synchro- — nous Input clock pulse SCKW Scyc width Input clock rise time — SCKr Input clock fall time — SCKf Transmit data delay — Figure 24.19 time Receive data setup —...
Page 724: Figure 24.12 I/O Port Input/Output Timing
φ Ports 1, 3, 4, 7, 9, A to G(read) Ports 1, 3, 7, A to G(write) Figure 24.12 I/O Port Input/Output Timing φ TOCD Output compare output* TICS Input capture input* Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 24.13 TPU Input/Output Timing φ...
Page 725: Figure 24.15 8-Bit Timer Output Timing
TMOD TMO0, TMO1 Figure 24.15 8-bit Timer Output Timing TMCS TMCS TMCI01 TMCWL TMCWH Figure 24.16 8-bit Timer Clock Input Timing TMRS TMRI01 Figure 24.17 8-bit Timer Reset Input Timing SCKW SCKr SCKf SCK0 to SCK2 Scyc Figure 24.18 SCK Clock Input Timing Rev.
Page 726: Figure 24.19 Sci Input/Output Timing (Clock Synchronous Mode)
SCK0 to SCK2 TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) Figure 24.19 SCI Input/Output Timing (Clock Synchronous Mode) φ TRGS Figure 24.20 A/D Converter External Trigger Input Timing tcyc TCKH TCKL Figure 24.21 Boundary Scan TCK Input Timing TRSS TRSS TRSW...
Page 727: Figure 24.23 Boundary Scan Data Transmission Timing
TDIS TDIH TMSS TMSH TDOD TDOD Figure 24.23 Boundary Scan Data Transmission Timing Rev. 3.0, 10/02, page 669 of 686...
Page 728: Ubs Characteristics
24.5 UBS Characteristics Table 24.8 lists the USB characteristics (USD+ and USD- pins) when the on-chip USB transceiver is used. Table 24.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver is Used Conditions: V = PLL V =Dr V =3.0 V to 3.6 V, V = PLLV = DrV...
Page 729: A/D Conversion Characteristics
R s = 24 USD+ Test Point = 50pF R s = 24 USD- Test Point = 50pF Figure 24.25 Test Load Circuit 24.6 A/D Conversion Characteristics Table 24.9 lists the A/D conversion characteristics. Table 24.9 A/D Conversion Characteristics Conditions: V = PLLV =DrV = 2.7 V to 3.6 V, AV...
Page 730: D/A Conversion Characteristics
24.7 D/A Conversion Characteristics Table 24.10 lists the D/A conversion characteristics. Table 24.10 D/A Conversion Characteristics Conditions: V = PLL V =Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV = PLLAV = 0 V, φ =13 MHz to 16 MHz, Dr V = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range...
Page 731: Usage Note
Item Symbol Unit Common Wait time after SWE1 bit setting* — θ Wait time after SWE1 bit clear* — Erase Wait time after ESU1 bit setting* — µs Wait time after E1 bit setting* α Wait time after E1 bit clear* —...
Page 732 Rev. 3.0, 10/02, page 674 of 686...
Page 733: Appendix
Appendix I/O Port States in Each Processing State Hardware Software Bus Right Program Port Name Operating Power-on Manual Standby Standby Release Execution State Pin Name Mode Reset Reset Mode Mode State or Sleep Mode P17 to P14 4 to 7 keep keep keep...
Page 734 Hardware Software Bus Right Program Port Name Operating Power-on Manual Standby Standby Release Execution State Pin Name Mode Reset Reset Mode Mode State or Sleep Mode Port B keep keep keep I/O port Address output 4 and 5 keep [OPE=0] Address output selected by AEn [OPE=1]...
Page 735 Hardware Software Bus Right Program Port Name Operating Power-on Manual Standby Standby Release Execution State Pin Name Mode Reset Reset Mode Mode State or Sleep Mode PF3/LWR keep keep keep I/O port 8 bit bus 4 to 6 (Mode 4) keep keep keep...
Page 736 [Legend] H: High level L: Low level T: High impedance keep : Input port level is high impedance, and output port level is retained. DDR : Data direction register OPE : Output port enable WAITE : Wait port enable BRLE : Bus release enable Note: *L (address input) in mode 4 or 5 Rev.
Page 737: Product Model Lineup
HD6432215C HD6432215C(***)TE 120 pin TQFP (TFP-120) HD6432215C(***)BR 112 pin P-LFBGA (BP-112) Legend (***) is ROM code. Note: The above list includes products under developing and planning. For the status for each product, please contact your Hitachi sales agency. Rev. 3.0, 10/02, page 679 of 686...
Page 738: Package Dimensions
Package Dimensions 16.0 ± 0.2 Unit: mm *0.17 ± 0.05 0.07 0.15 ± 0.04 ˚ - ˚ 0.5 ± 0.1 0.10 Hitachi Code TFP-120  JEDEC EIAJ ED-7404A *Dimension including the plating thickness Base material dimension Mass (reference value) 0.5 g Figure C.1 TFP-120 Package Dimension...
Page 739: Figure C.2 Bp-112 Package Dimension
0.20 C A 11 10 9 4 × 0.15 0.80 1.00 112 × φ0.50 ± 0.05 φ0.08 0.10 Hitachi Code BP-112 JEDEC – JEITA – Mass (reference value) 0.3 g Figure C.2 BP-112 Package Dimension Rev. 3.0, 10/02, page 681 of 686...
Page 740 Rev. 3.0, 10/02, page 682 of 686...
Page 741: Index
Index Bus Arbitration........138 16-Bit Timer Pulse Unit......263 bus cycle..........116 Buffer Operation ......... 299 Free-running count operation....293 Clock Pulse Generator ......595 Input Capture Function ....... 296 Condition Field .........45 periodic count operation ..... 293 Condition-Code Register......30 Phase Counting Mode......305 CPU Operating Modes ......22 PWM Modes........
Page 742 Hardware Protection ......587 Operating Mode Selection ......55 Program/Program-Verify ....583 Operation Field ......... 45 Programmer Mode ......588 programming units......563 PLL Circuit ..........603 Programming/Erasing in User Program Port A Open Drain Control Register ..235 Mode........... 580 port register ..........
Page 743 MDCR........56, 635, 643 PORTF ........ 257, 641, 648 MRA ........197, 634, 643 PORTG ....... 260, 641, 648 MRB ........198, 634, 643 RAMER ......569, 637, 645 MSTPCR ......612, 635, 643 RDR ........362, 640, 647 MSTPCRB.......... 481 RSR .............361 P1DDR........
Page 744: Section 12 Watchdog Timer
UEDR4o ......460, 633, 642 UEDR5i ......460, 633, 642 Serial Communication Interface ..... 357 UEPIR......... 438, 633, 642 Asynchronous Mode ......381 UESTL0......455, 633, 642 Bit Rate ..........375 UESTL1......456, 633, 642 Break........... 409 UESZ0o ......460, 633, 642 framing error ........
Page 745 Publication Date: 1st Edition, April 2001 3rd Edition, October 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.

Hitachi H8S/2215 Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 6 Bus Controller

Section 7 DMA Controller

Section 7 DMA Controller

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Summary of Contents for Hitachi H8S/2215 Series