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FIFO Output Pattern Register 2 (FPDRB)
Bit :
15
—
Initial value :
—
R/W :
Bit :
PPGB7
Initial value :
R/W :
W
Note : * Don't care
FPDRB is a buffer register for the FIFO2 output pattern register. The output pattern data written
in FPDRB is written at the same time to the position of the FIFO2 pointed by the buffer pointer.
Be sure to write the output pattern data in FPDRB before writing it in FTPRB.
FPDRB is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted,
correct operation is not guaranteed. No read is valid. If a read is attempted, an undetermined
value is read out. It is not initialized by a reset, or in stand-by or module stop mode; accordingly
be sure to write data before use.
Bit 15 Reserved: Cannot be read or modified.
Bit 14 A/D Trigger B Bit (ADTRGB): Indicates a hardware trigger signal for the A/D
converter.
Bit 13 S-TRIGB Bit (STRIGB): Indicates a signal that generates an interrupt. When the
STRIGA is selected by the ISEL, modifying this bit from 0 to 1 generates an interrupt.
Bit 12 NarrowFFB Bit (NarrowFFB): Controls the narrow video head.
Bit 11 VideoFFB Bit (VFFB): Controls the video head.
Bit 10 AudioFFB Bit (AFFB): Controls the audio head.
Bit 9 VpulseB Bit (VpulseB): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bit 8 MlevelB Bit (MlevelB): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bits 7 to 0 PPG Output Signal B Bits (PPGB7 to PPGB0): Used for outputting a timing
control signal from port 7 (PPG).
14
13
ADTRGB
STRIGB
1
*
W
W
7
6
PPGB6
PPGB5
*
*
W
W
12
11
NarrowFFB
VFFB
*
*
W
W
5
4
PPGB4
PPGB3
*
*
W
W
10
AFFB
VpulseB
*
*
W
W
3
2
PPGB2
PPGB1
*
*
W
W
Rev. 1.0, 02/00, page 601 of 1141
9
8
MlevelB
*
*
W
1
0
PPGB0
*
*
W
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