Module Stop Control Register (Mstpcr) - Hitachi H8S/2199 Hardware Manual

When reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in
subactive mode, or in subsleep mode, the SDATA register values are indeterminate.
28.2.5

Module Stop Control Register (MSTPCR)

Bit: 7
MSTP
15
Initial value: 1
R/W
R/W:
The MSTPCR consists of two 8-bit read/write registers for controlling the module stop mode.
Writing 0 to the MSTP3 bit starts the data slicer; setting the MSTP3 bit to 1 stops the data slicer at
the end of a bus cycle and the module stop mode is entered. Before writing 0 to this bit, set the
MSTP9 bit to 0, to operate the sync separator.
The registers cannot be read or written to in module stop mode. For details, refer to section 4.5,
Module Stop Mode.
Bit 3    Module Stop (MSTP3): Specifies the module stop mode for the data slicer.
Bit 3
MSTP3 Description
0 Clears the module stop mode for the data slicer
1 Specifies the module stop mode for the data slicer
Rev. 1.0, 02/00, page 812 of 1141
MSTPCRH
6 5 4 3
MSTP MSTP MSTP MSTP
14 13 12 11
1 1 1 1
R/W R/W R/W R/W
2 1 0 7
MSTP MSTP MSTP MSTP
10 9 8 7
1 1 1 1
R/W R/W R/W R/W
MSTPCRL
6 5 4 3
MSTP MSTP MSTP MSTP
6 5 4 4
1 1 1 1
R/W R/W R/W R/W
2 1 0
MSTP MSTP MSTP
1 0
1 1 1
R/W R/W R/W
(Initial value)