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26.13.10 Trapezoid Waveform Circuit
In rewriting, the trapezoid waveform circuit leaves the rising edge of the already-recorded PB-
CTL signal intact, but changes the duty cycle.
In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle
for a rewrite is set in the REC-CTL duty data registers (RCDR2 to RCDR5). Time values T2 to
T5 are referenced to the rise of PB-CTL.
Figure 26.62 shows the rewrite waveform.
RESET
PB-CTL↑
φs/4
PB-CTL
REC-CTL when
rewriting
Figure 26.62 Relationship between REC-CTL and RCDR2 to RCDR5 when Rewriting
Rev. 1.0, 02/00, page 716 of 1141
Clear
Up/Down counter (16 bits)
Upper 12 bits
REC-CTL 1 pulse
Eliminated
pulse
T
2
Internal bus
W
RCDR2or4
RCDR3or5
(12 bits)
(12 bits)
Compare
Compare
fall timing
New pulse
to T
5
RCDR2 (BISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
W
W
RCDR1
(12 bits)
Not used when
rewriting
REC-CTL 0 pulse
fall timing
End of writing of one
CTL pulse (except
VISS) IRRCTL
High-impedance
interval
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