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H'D111: Timer Load RegisterB TLB: TimerB
Bit :
Initial value :
R/W :
H'D112: Timer L Mode Register LMR: Timer L
7
Bit
:
LMIF
Initial value
:
0
R/W
:
R/(W)*
Timer L interrupt request flag
0
1
Note: * Only 0 can be written to clear the flag.
Rev. 1.0, 02/00, page 1044 of 1141
7
6
TLB17
TLB16
TLB15
0
0
W
W
6
5
LMIE
—
0
1
R/W
—
Clock select bit
LMR2
0
1
Note: * Don't care.
Up/down count control
0
Up count control
1
Down count control
Timer L interrupt enable bit
0
Timer L interrupt request is disabled
1
Timer L interrupt request is enabled
[Clearing conditions]
When 0 is written after reading 1
[Setting conditions]
When LTC overflow, underflow or compare
match clear occurs
5
4
3
TLB14
TLB13
0
0
0
W
W
W
4
3
LMR3
—
1
0
R/W
—
LMR1
LMR0
0
0
1
1
*
0
*
1
*
(Initial value)
(Initial value)
2
1
TLB12
TLB11
0
0
W
W
2
1
LMR2
LMR1
LMR0
0
0
R/W
R/W
R/W
Clock select
Count at rising edge of PB and REC-CTL
Count at falling edge of PB and REC-CTL
Count DVCFG2
Internal clock: Count at φ/128
Internal clock: Count at φ/64
(Initial value)
0
TLB10
0
W
0
0
(Initial value)
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