Page 1 To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Page 2 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Page 3 Hitachi 16-bit Single-Chip Microcomputer H8S/2628 Series H8S/2628 HD64F2628, HD6432628 H8S/2627 HD6432627 Hardware Manual ADE-602-278 Rev. 1.0 09/13/02 Hitachi, Ltd.
Page 4 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 5: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 6 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 7: Preface
Note:* F-ZTAT is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2628 Series in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 8 ADE No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor ADE-702-247 User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-282 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging ADE-702-231 Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-201 xxxvi Rev. 1.0, 09/02, page...
Page 9: Table Of Contents
Contents Section 1 Overview................... 1 Overview...........................1 Internal Block Diagram..................... 2 Pin Arrangement .......................3 Pin Functions ........................4 Section 2 CPU....................9 Features ..........................9 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........10 2.1.2 Differences from H8/300 CPU................11 2.1.3 Differences from H8/300H CPU................11 CPU Operating Modes ......................12 2.2.1 Normal Mode.......................12...
Page 10 Usage Note........................45 2.9.1 Notes on Using the Bit Operation Instruction............45 Section 3 MCU Operating Modes ..............47 Operating Mode Selection ....................47 Register Descriptions ......................47 3.2.1 Mode Control Register (MDCR) ................. 48 3.2.2 System Control Register (SYSCR) ..............49 Pin Functions in Each Operating Mode ................
Page 11 5.7.1 Conflict between Interrupt Generation and Disabling .........82 5.7.2 Instructions that Disable Interrupts ..............83 5.7.3 When Interrupts Are Disabled ................83 5.7.4 Interrupts during Execution of EEPMOV Instruction..........84 Section 6 PC Break Controller (PBC) .............. 85 Features ..........................85 Register Descriptions ......................86 6.2.1 Break Address Register A (BARA) ..............86 6.2.2...
Page 12 8.2.1 DTC Mode Register A (MRA) ................100 8.2.2 DTC Mode Register B (MRB)................101 8.2.3 DTC Source Address Register (SAR)..............101 8.2.4 DTC Destination Address Register (DAR)............101 8.2.5 DTC Transfer Count Register A (CRA) .............. 101 8.2.6 DTC Transfer Count Register B (CRB)............... 102 8.2.7 DTC Enable Registers (DTCER) .................
Page 13 9.3.1 Port 4 Register (PORT4)..................133 Port 7..........................133 9.4.1 Port 7 Data Direction Register (P7DDR).............134 9.4.2 Port 7 Data Register (P7DR)................134 9.4.3 Port 7 Register (PORT7)..................134 9.4.4 Pin Functions .......................135 Port 9..........................136 9.5.1 Port 9 Register (PORT9)..................136 Port A ..........................138 9.6.1 Port A Data Direction Register (PADDR) ............138 9.6.2 Port A Data Register (PADR) ................139...
Page 14 10.2 Input/Output Pins ......................163 10.3 Register Descriptions ......................164 10.3.1 Timer Control Register (TCR)................166 10.3.2 Timer Mode Register (TMDR) ................171 10.3.3 Timer I/O Control Register (TIOR) ..............173 10.3.4 Timer Interrupt Enable Register (TIER) .............. 190 10.3.5 Timer Status Register (TSR)................192 10.3.6 Timer Counter (TCNT)..................
Page 15 11.3 Register Descriptions ......................243 11.3.1 Timer Counters (TCNT) ..................244 11.3.2 Time Constant Registers A (TCORA) ..............244 11.3.3 Time Constant Registers B (TCORB)..............244 11.3.4 Timer Control Registers (TCR) ................244 11.3.5 Timer Control/Status Registers (TCSR) ..............247 11.4 Operation...........................251 11.4.1 Pulse Output......................251 11.5 Operation Timing......................252 11.5.1 TCNT Incrementation Timing ................252 11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs....253 11.5.3 Timing of Timer Output When a Compare-Match Occurs ........254...
Page 16 12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)..275 12.4.5 Non-Overlapping Pulse Output................276 12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output ......278 12.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)....279 12.4.8 Inverted Pulse Output ..................
Page 17 14.9.2 Break Detection and Processing................353 14.9.3 Mark State and Break Detection ................353 14.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..............353 Section 15 Hitachi Controller Area Network (HCAN)........355 15.1 Features ..........................355 15.2 Input/Output Pins ......................357 15.3 Register Descriptions ......................357 15.3.1 Master Control Register (MCR)................358...
Page 18 15.3.4 Mailbox Configuration Register (MBCR) ............363 15.3.5 Transmit Wait Register (TXPR) ................364 15.3.6 Transmit Wait Cancel Register (TXCR).............. 365 15.3.7 Transmit Acknowledge Register (TXACK) ............366 15.3.8 Abort Acknowledge Register (ABACK) ............. 367 15.3.9 Receive Complete Register (RXPR)..............368 15.3.10 Remote Request Register (RFPR)................
Page 19 16.3.1 SS Control Register H (SSCRH)................407 16.3.2 SS Control Register L (SSCRL) ................409 16.3.3 SS Mode Register (SSMR) ..................410 16.3.4 SS Enable Register (SSER)..................411 16.3.5 SS Status Register (SSSR) ...................412 16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3) ........415 16.3.7 SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3)........415 16.3.8 SS Shift Register (SSTRSR) ................415 16.4 Operation...........................416...
Page 20 19.1 Features..........................445 19.2 Mode Transitions ......................446 19.3 Block Configuration......................450 19.4 Input/Output Pins ......................451 19.5 Register Descriptions ......................451 19.5.1 Flash Memory Control Register 1 (FLMCR1)............. 452 19.5.2 Flash Memory Control Register 2 (FLMCR2)............. 453 19.5.3 Erase Block Register 1 (EBR1) ................453 19.5.4 Erase Block Register 2 (EBR2) ................
Page 21 21.2 Medium-Speed Mode......................483 21.3 Sleep Mode ........................484 21.3.1 Transition to Sleep Mode..................484 21.3.2 Clearing Sleep Mode....................484 21.4 Software Standby Mode....................485 21.4.1 Transition to Software Standby Mode ..............485 21.4.2 Clearing Software Standby Mode ................485 21.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode...486 21.4.4 Software Standby Mode Application Example............487 21.5 Hardware Standby Mode....................488 21.5.1 Transition to Hardware Standby Mode ..............488...
Page 22 Index ......................565 xxxvi Rev. 1.0, 09/02, page...
Page 23 Figures Section 1 Overview Figure 1.1 Internal Block Diagram ....................2 Figure 1.2 Pin Arrangement......................3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ..............13 Figure 2.2 Stack Structure in Normal Mode .................13 Figure 2.3 Exception Vector Table (Advanced Mode) ..............14 Figure 2.4 Stack Structure in Advanced Mode ................15 Figure 2.5 Memory Map .......................16 Figure 2.6 CPU Registers ......................17...
Page 24 Figure 6.2 Operation in Power-Down Mode Transitions.............. 89 Section 7 Bus Controller Figure 7.1 On-Chip Memory Access Cycle.................. 93 Figure 7.2 On-Chip Support Module Access Cycle..............94 Figure 7.3 On-Chip HCAN Module Access Cycle (with Wait States) ......... 94 Figure.7.4 On-chip SSU Module Access Cycle................95 Section 8 Data Transfer Controller (DTC) Figure 8.1 Block Diagram of DTC ....................
Page 25 Figure 10.21 Example of PWM Mode Operation (1) ..............212 Figure 10.22 Example of PWM Mode Operation (2) ..............212 Figure 10.23 Example of PWM Mode Operation (3) ..............213 Figure 10.24 Example of Phase Counting Mode Setting Procedure...........214 Figure 10.25 Example of Phase Counting Mode 1 Operation ............215 Figure 10.26 Example of Phase Counting Mode 2 Operation ............216 Figure 10.27 Example of Phase Counting Mode 3 Operation ............217 Figure 10.28 Example of Phase Counting Mode 4 Operation ............218...
Page 26 Figure 11.9 Timing of OVF Setting.................... 255 Figure 11.10 Conflict between TCNT Write and Clear .............. 258 Figure 11.11 Conflict between TCNT Write and Increment ............259 Figure 11.12 Conflict between TCOR Write and Compare-Match ..........259 Section 12 Programmable Pulse Generator (PPG) Figure 12.1 Block Diagram of PPG....................
Page 27 Figure 14.30 Example of Reception Processing Flow ..............349 Figure 14.31 Timing for Fixing Clock Output Level..............349 Figure 14.32 Clock Halt and Restart Procedure................350 Section 15 Hitachi Controller Area Network (HCAN) Figure 15.1 HCAN Block Diagram ....................356 Figure 15.2 Message Control Register Configuration ..............380 Figure 15.3 Standard Format ......................380...
Page 28 Figure 16.1 Block Diagram of SSU.................... 406 Figure 16.2 Relationship of Clock Phase, Polarity, and Data ............. 416 Figure 16.3 Relationship between Data I/O Pins and the Shift Register ........417 Figure 16.4 Example of SSU Initialization................. 418 Figure 16.5 Example of Transmission Operation ............... 419 Figure 16.6 Example of Data Transmission Flowchart ..............
Page 29: Electrical Characteristics
Section 21 Power-Down Modes Figure 21.1 Mode Transition Diagram ..................478 Figure 21.2 Medium-Speed Mode Transition and Clearance Timing.........484 Figure 21.3 Software Standby Mode Application Example ............487 Figure 21.4 Timing of Transition to Hardware Standby Mode...........488 Figure 21.5 Timing of Recovery from Hardware Standby Mode ..........489 Section 23 Electrical Characteristics Figure 23.1 Output Load Circuit....................548 Figure 23.2 System Clock Timing ....................549...
Page 30 Rev. 1.0, 09/02, page xxviii of xxxiv...
Page 31 Tables Section 2 CPU Table 2.1 Instruction Classification ....................25 Table 2.2 Operation Notation......................26 Table 2.3 Data Transfer Instructions...................27 Table 2.4 Arithmetic Operations Instructions (1) ...............28 Table 2.4 Arithmetic Operations Instructions (2) ...............29 Table 2.5 Logic Operations Instructions ..................30 Table 2.6 Shift Instructions......................31 Table 2.7 Bit Manipulation Instructions (1)................32...
Page 32 Section 9 I/O Ports Table 9.1 Port Functions ......................122 Table 9.2 P17 Pin Function....................... 127 Table 9.3 P16 Pin Function....................... 127 Table 9.4 P15 Pin Function....................... 127 Table 9.5 P14 Pin Function....................... 128 Table 9.6 P13 Pin Function....................... 128 Table 9.7 P12 Pin Function.......................
Page 33 Table 9.43 PC2 Pin Function ....................150 Table 9.44 PC1 Pin Function ....................151 Table 9.45 PC 0Pin Function ....................151 Table 9.46 PF7 Pin Function....................157 Table 9.47 PF6 Pin Function....................157 Table 9.48 PF5 Pin Function....................157 Table 9.49 PF4 Pin Function....................157 Table 9.50 PF3 Pin Function....................157 Table 9.51 PF2 Pin Function....................157...
Page 34 SSR Status Flags and Receive Data Handling ............323 Table 14.12 SCI Interrupt Sources.................... 351 Table 14.13 SCI Interrupt Sources.................... 352 Section 15 Hitachi Controller Area Network (HCAN) Table 15.1 HCAN Pins ......................357 Table 15.2 Limits for the Settable Value ................387 Table 15.3...
Page 35 Table 15.4 HCAN Interrupt Sources..................400 Section 16 Synchronous Serial Communication Unit (SSU) Table 16.1 Pin Configuration....................407 Table 16.2 Interrupt Souses ....................426 Section 17 A/D Converter Table 17.1 Pin Configuration....................429 Table 17.2 Analog Input Channels and Corresponding ADDR Registers ......430 Table 17.3 A/D Conversion Time (Single Mode)..............436 Table 17.4 A/D Conversion Time (Scan Mode) ..............436...
Page 36 Table 23.9 Flash Memory Characteristics ................561 Rev. 1.0, 09/02, page xxxiv of xxxiv...
Page 37: Section 1 Overview
 8-bit timer (TMR)  Programmable pulse generator (PPG)  Watchdog timer  Asynchronous or clocked synchronous serial communication interface (SCI)  Hitachi controller area network (HCAN)  Synchronous serial communication unit (SSU)  10-bit A/D converter  Clock pulse generator •...
Page 38: Internal Block Diagram
Internal Block Diagram Port D PA3/SCK2 PA2/RxD2 EXTAL PA1/TxD2 XTAL PLLCAP PLLVSS H8S/2600 CPU PB7/TIOCB5 PB6/TIOCA5 FWE/NC * PB5/TIOCB4 PB4/TIOCA4 Interrupt controller PB3/TIOCD3 PB2/TIOCC3 PB1/TIOCB3 PF7/φ PC break controller PB0/TIOCA3 (2 channels) PC7/ PC6/SSCK1 WDT × 1 channel PF3/ PC5/SSI1 (Masked ROM, PC4/SSO1 flash memory)
Page 39: Pin Arrangement
Pin Arrangement 75747372717069686766656463626160595857565554535251 P97/AN15 P32/SCK0/ P96/AN14 P95/AN13 P94/AN12 P35/ P93/AN11 P92/AN10 P91/AN9 PA3/SCK2 P90/AN8 PA2/RxD2 AVSS PA1/TxD2 Vref PB7/TIOCB5 AVCC FP-100M PB6/TIOCA5 P47/AN7 (Top view) PB5/TIOCB4 P46/AN6 PB4/TIOCA4 P45/AN5 P44/AN4 PB3/TIOCD3 P43/AN3 PB2/TIOCC3 P42/AN2 P41/AN1 PB1/TIOCB3 P40/AN0 P10/PO8/TIOCA0 PB0/TIOCA3 P11/PO9/TIOCB0 PC7/ P12/PO10/TIOCC0/TCLKA PC6/SSCK1...
Page 40: Pin Functions
Pin Functions Type Symbol Pin NO. Function Power Input Power supply pins. Connect all these pins to the Supply system power supply. Input Ground pins. Connect all these pins to the system power supply (0 V). Output External capacitance pin for internal power-down power supply.
Page 41 Type Symbol Pin NO. Function Interrupts Input Nonmaskable interrupt pin. If this pin is not used, it should be fixed high. IRQ5 Input These pins request a maskable interrupt. IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 16-bit TCLKA Input These pins input an external clock. timer- TCLKB pulse unit...
Page 42 Type Symbol Pin NO. Function 8-bit timer TMRI23 Input Counter reset input pins (TMR) TMRI01 Serial TxD2 Output Data output pins communi- TxD0 cation RxD2 Input Data input pins Interface RxD0 (SCI)/ SCK2 Input/ Clock input/output pins smart card SCK0 Output interface HCAN...
Page 43 Type Symbol Pin NO. Function Vref Input The reference voltage input pin for the A/D converter converter. When the A/D converter is not used, connect this pin to the system power supply (+5 I/O ports Input/ Eight input/output pins Output Input/ Eight input/output pins Output...
Page 44 Type Symbol Pin NO. Function I/O ports Input/ Four input/output pins Output Input/ Eight input/output pins Output Input/ Eight input/output pins Output Input/ Eight input/output pins Output Input/ Eight input/output pins Output Rev. 1.0, 09/02, page 8 of 568...
Page 45: Section 2 Cpu
Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU.
Page 46: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
• Two CPU operating modes  Normal mode*  Advanced mode • Power-down state  Transition to power-down state by the SLEEP instruction  CPU clock speed selection Note:* Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
Page 47: Differences From H8/300 Cpu
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: • More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added.
Page 48: Cpu Operating Modes
CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU.
Page 49: Advanced Mode
H'0000 Exception vector 1 H'0001 H'0002 Exception vector 2 H'0003 H'0004 Exception vector 3 H'0005 H'0006 Exception Exception vector 4 vector table H'0007 H'0008 Exception vector 5 H'0009 H'000A Exception vector 6 H'000B Figure 2.1 Exception Vector Table (Normal Mode) EXR* (16 bits) Reserved*...
Page 50: Figure 2.3 Exception Vector Table (Advanced Mode)
• Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H′00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3).
Page 51: Figure 2.4 Stack Structure In Advanced Mode
EXR* Reserved Reserved* (24 bits) (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode Rev.
Page 52: Address Space
Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 53: Registers
Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
Page 54: General Registers
2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 55: Program Counter (Pc)
Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Page 56: Condition-Code Register (Ccr)
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 57: Multiply-Accumulate Register (Mac)
Bit Name Initial Value Description undefined Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. undefined Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: •...
Page 58: Data Formats
Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 59: Figure 2.9 General Register Data Formats (2)
Data Type Register Number Data Format Word data Word data Longword data Legend : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 60: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address.
Page 61: Instruction Set
Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L operations ADDX, SUBX, DAA, DAS...
Page 62: Table Of Instructions Classified By Function
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register)
Page 63: Table 2.3 Data Transfer Instructions
Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI. MOVTPE Cannot be used in this LSI.
Page 64: Table 2.4 Arithmetic Operations Instructions (1)
Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register.
Page 65: Table 2.4 Arithmetic Operations Instructions (2)
Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 66: Table 2.5 Logic Operations Instructions
Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 67: Table 2.6 Shift Instructions
Table 2.6 Shift Instructions Instruction Size* Function Rd (shift) → Rd SHAL B/W/L SHAR Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (shift) → Rd SHLL B/W/L SHLR Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible.
Page 68: Table 2.7 Bit Manipulation Instructions (1)
Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 69: Table 2.7 Bit Manipulation Instructions (2)
Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. ∼...
Page 70: Table 2.8 Branch Instructions
Table 2.8 Branch Instructions Instruction Size Function  Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 71: Table 2.9 System Control Instructions
Table 2.9 System Control Instructions Instruction Size* Function  TRAPA Starts trap-instruction exception handling.  Returns from an exception-handling routine.  SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves general register or memory contents or immediate data to CCR or EXR.
Page 72: Basic Instruction Formats
Table 2.10 Block Data Transfer Instructions Instruction Size Function  if R4L ≠ 0 then EEPMOV.B Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next;  if R4 ≠ 0 then EEPMOV.W Repeat @ER5+ → @ER6+ R4–1 →...
Page 73: Figure 2.11 Instruction Formats (Examples)
• Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. •...
Page 74: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
Page 75: Register Indirect With Post-Increment Or Pre-Decrement@Ern+ Or @-Ern
Register Indirect with Post-Increment or Pre-Decrement    @ERn+ or @-ERn 2.7.4 Register indirect with post-increment    @ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
Page 76: Immediate#Xx:8, #Xx:16, Or #Xx:32
Immediate    #xx:8, #xx:16, or #xx:32 2.7.6 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number.
Page 77: Effective Address Calculation
Specified Specified Reserved Branch address by @aa:8 by @aa:8 Branch address (a) Normal Mode (a) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode.
Page 78 Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct(Rn) Operand is general register contents. Register indirect(@ERn) General register contents General register contents Sign extension Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ General register contents 1, 2, or 4...
Page 79 Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Note: * Normal mode is not available in this LSI. Rev.
Page 80: Processing States
Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 81: Usage Note
Reset state Exception handling state Bus-released state Request for End of End of exception exception request bus request handling handling Program execution state Program halt state SLEEP instruction Notes: From any state, a transition to hardware standby mode occurs when goes low.
Page 82 Rev. 1.0, 09/02, page 46 of 568...
Page 83: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Operating Mode Selection This LSI supports only operating mode 7, that is, the advanced single-chip mode. The operating mode is determined by the setting of the mode pins (MD2 to MD0). Only mode 7 can be used in this LSI.
Page 84: Mode Control Register (Mdcr)
3.2.1 Mode Control Register (MDCR) Bit Name Initial Descriptions Value  Reserved Only 1 should be written to this bit.   All 0 Reserved These bits are always read as 0 and cannot be modified.  MDS2 Mode select 2 to 0 ...
Page 85: System Control Register (Syscr)
3.2.2 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM. Bit Name Initial Descriptions Value...
Page 86: Pin Functions In Each Operating Mode
Pin Functions in Each Operating Mode The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, however external addresses cannot be accessed. All I/O ports are available for use as input-output ports. Rev. 1.0, 09/02, page 50 of 568...
Page 87: Address Map
Address Map Figure 3.1 shows the address map in each operating mode. H8S/2628 H8S/2627 ROM: 128 kbytes, RAM: 8 kbytes ROM: 96 kbytes, RAM: 6 kbytes Mode 7 Mode 7 Advanced single-chip mode Advanced single-chip mode H'000000 H'000000 On-chip ROM...
Page 88 Rev. 1.0, 09/02, page 52 of 568...
Page 89: Section 4 Exception Handling
Section 4 Exception Handling Exception Handling Types and Priority As shown in table 4.1, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 90: Table 4.2 Exception Handling Vector Table
Table 4.2 Exception Handling Vector Table Vector Address* Exception Source Vector Number Normal Mode Advanced Mode Power-on reset H′0000 to H′0001 H′0000 to H′0003 Manual reset * H′0002 to H′0003 H′0004 to H′0007 Reserved for system use H′0004 to H′0005 H′0008 to H′000B H′0006 to H′0007 H′000C to H′000F...
Page 91: Reset
Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states.
Page 92: Figure 4.1 Reset Sequence (Advanced Mode With On-Chip Rom Enabled)
Fetch of first Internal Vector fetch program instruction processing φ Internal address bus Internal read signal Internal write High signal Internal data (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
Page 93: Interrupts After Reset
Internal Fetch of first processing program instruction Vector fetch φ Address bus High D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note:* Three program wait states are inserted.
Page 94: Traces
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
Page 95: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack.
Page 96: Stack Status After Exception Handling
Stack Status after Exception Handling Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes Reserved* CCR* CCR* PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes Reserved* PC (24 bits)
Page 97: Usage Note
Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
Page 98 Rev. 1.0, 09/02, page 62 of 568...
Page 99: Section 5 Interrupt Controller
Section 5 Interrupt Controller Features • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR  An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
Page 100: Figure 5.1 Block Diagram Of Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request SWDTEND to SSERT_i1 I2 to I0 Interrupt controller Legend : IRQ sense control register...
Page 101: Input/Output Pins
Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name Function Input Nonmaskable external interrupt Rising or falling edge can be selected IRQ5 Input Maskable external interrupts IRQ4 Input Rising, falling, or both edges, or level sensing, can be selected IRQ3 Input IRQ2...
Page 102: Interrupt Priority Registers A To M (Ipra To Iprm)
5.3.1 Interrupt Priority Registers A to M (IPRA to IPRM) The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H′0 to H′7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt.
Page 103: Irq Enable Register (Ier)
5.3.2 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that controls the enabling and disabling of interrupt requests IRQ0 to IRQ5. Bit Name Initial Value Description  All 0 Reserved Only 0 should be written to these bits. IRQ5E IRQ5 Enable The IRQ5 interrupt request is enabled when this...
Page 104: Irq Sense Control Registers H And L (Iscrh, Iscrl)
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL) The ISCR registers are 16-bit readable/writable registers that select the source that generates an interrupt request at pins IRQ0 to IRQ5. • ISCRH Bit Name Initial Value Description  15 to All 0 Reserved Only 0 should be written to these bits.
Page 105 • ISCRL Bit Name Initial Value Description IRQ3SCB IRQ3 Sense Control B IRQ3SCA IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input level low 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input...
Page 106: Irq Status Register (Isr)
5.3.4 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt requests. Bit Name Initial Value Description  All 0 Reserved Only 0 should be written to these bits. IRQ5F [Setting conditions] IRQ4F When the interrupt source selected by the ISCR IRQ3F...
Page 107: Interrupt Sources
Interrupt Sources 5.4.1 External Interrupts There are seven external interrupts: NMI and IRQ0 to IRQ5. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
Page 108: Internal Interrupts
5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller.
Page 109: Table 5.2 Interrupt Sources, Vector Addresses, And Interrupt Priorities
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Interrupt Origin of Vector Advanced Source Interrupt Source Number Mode Priority External H′001C High IRQ0 H′0040 IPRA6 to IPRA4 IRQ1 H′0044 IPRA2 to IPRA0 IRQ2 H′0048 IPRB6 to IPRB4 IRQ3 H′004C IRQ4...
Page 110 Vector Address* Interrupt Origin of Vector Advanced Source Interrupt Source Number Mode Priority TGIA_3 H′00C0 IPRG2 to IPRG0 High channel 3 TGIB_3 H′00C4 TGIC_3 H′00C8 TGID_3 H′00CC TCIV_3 H′00D0 TGIA_4 H′00E0 IPRH6 to IPRH4 channel 4 TGIB_4 H′00E4 TCIV_4 H′00E8 TCIU_4 H′00EC TGIA_5...
Page 111 Vector Address* Interrupt Origin of Vector Advanced Source Interrupt Source Number Mode Priority 8-bit timer CMIA_2 H′0170 IPRL6 to IPRL4 High channel 2 CMIB_2 H′0174 OVI_2 H′0178 8-bit timer CMIA_3 H′0180 channel 3 CMIB_3 H′0184 OVI_3 H′0188 HCAN ERS0, OVR0 H′01A0 IPRM6 to IPRM4 H′01A4...
Page 112: Interrupt Control Modes And Interrupt Operation
Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
Page 113: Figure 5.3 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 0
Program execution status Interrupt generated? I = 0 Hold pending IRQ0 IRQ1 SSERT_i1 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.
Page 114: Interrupt Control Mode 2
5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
Page 115: Interrupt Exception Handling Sequence
Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Hold Save PC, CCR, and EXR pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2...
Page 116: Figure 5.5 Interrupt Exception Handling
Figure 5.5 Interrupt Exception Handling Rev. 1.0, 09/02, page 80 of 568...
Page 117: Interrupt Response Times
5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Page 118: Dtc Activation By Interrupt
Table 5.5 Number of States in Interrupt Handling Routine Execution Status Object of Access External Device * 8-Bit Bus 16-Bit Bus Internal 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Instruction fetch 6+2m Branch address read Stack manipulation Legend : Number of wait states in an external device access.
Page 119: Instructions That Disable Interrupts
TIER_0 write cycle by CPU TCIVexception handling φ Internal TIER_0 address address bus Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.6 Conflict between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed.
Page 120: Interrupts During Execution Of Eepmov Instruction
5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle.
Page 121: Section 6 Pc Break Controller (Pbc)
Section 6 PC Break Controller (PBC) The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is shown in figure 6.1.
Page 122: Register Descriptions
BARA BCRA Mask control Control Comparator logic Internal address PC break Access interrupt status Control Comparator logic Match signal Mask control BARB BCRB Figure 6.1 Block Diagram of PC Break Controller Register Descriptions The PC break controller has the following registers. •...
Page 123: Break Address Register B (Barb)
6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) BCRA controls channel A PC breaks. BCRA also contains a condition match flag. Bit Name Initial Value Description...
Page 124: Break Control Register B (Bcrb)
6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A.
Page 125: Pc Break Operation At Consecutive Data Transfer
6.3.3 PC Break Operation at Consecutive Data Transfer • When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. •...
Page 126: When Instruction Execution Is Delayed By One State
6.3.5 When Instruction Execution Is Delayed by One State While the break interrupt enable bit is set to 1, instruction execution is one state later than usual. • For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip ROM or RAM.
Page 127: Usage Notes
Usage Notes 6.4.1 Module Stop Mode Setting PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 6.4.2 PC Break Interrupts The PC break interrupt is shared by channels A and B.
Page 128: Pc Break Set For Instruction Fetch At Address Following Bcc Instruction
6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, and is not generated if the instruction at the next address is not executed.
Page 129: Section 7 Bus Controller
Section 7 Bus Controller The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip support modules. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC).
Page 130: On-Chip Support Module Access Timing
7.1.2 On-Chip Support Module Access Timing The on-chip support modules, except for the HCAN, SSU, and realtime input port data register, are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed.
Page 131: On-Chip Ssu Module And Realtime Input Port Data Register Access Timing
7.1.4 On-chip SSU Module and Realtime Input Port Data Register Access Timing The on-chip SSU module or realtime input port data register is accessed in three states. At this time, a data bus width is 16 bits. Figure 7.4 shows the SSU module access timing. Bus cycle φ...
Page 132: Bus Transfer Timing
7.2.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus mastership and is currently operating, the bus mastership is not necessarily transferred immediately.
Page 133: Section 8 Data Transfer Controller (Dtc)
Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1.
Page 134: Figure 8.1 Block Diagram Of Dtc
Internal address bus On-chip Interrupt controller Interrupt request CPU interrupt Internal data bus request Legend : DTC mode registers A and B MRA, MRB : DTC transfer count registers A and B CRA, CRB : DTC source address register : DTC destination address register : DTC enable registers A to G DTCERA to DTCERG : DTC vector register...
Page 135: Register Descriptions
Register Descriptions The DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) • DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
Page 136: Dtc Mode Register A (Mra)
8.2.1 DTC Mode Register A (MRA) MRA is an 8-bit register that selects the DTC operating mode. Bit Name Initial Value Description  Undefined Source Address Mode 1 and 0  Undefined These bits specify an SAR operation after a data transfer.
Page 137: Dtc Mode Register B (Mrb)
8.2.2 DTC Mode Register B (MRB) MRB is an 8-bit register that selects the DTC operating mode. Bit Name Initial Value Description  CHNE Undefined DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed.
Page 138: Dtc Transfer Count Register B (Crb)
8.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H′0000.
Page 139: Dtc Vector Register (Dtvecr)
8.2.8 DTC Vector Register (DTVECR) DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Name Initial Value Description SWDTE DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit.
Page 140: Location Of Register Information And Dtc Vector Table
Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request DTVECR Interrupt controller Interrupt mask Figure 8.2 Block Diagram of DTC Activation Source Control Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H′FFEBC0 to H′FFEFBF). Register information should be located at an address that is a multiple of four within the range.
Page 141: Figure 8.3 Location Of Dtc Register Information In Address Space
Lower address Register information start address Register information Chain transfer Register information for 2nd transfer in chain transfer 4 bytes Figure 8.3 Location of DTC Register Information in Address Space Rev. 1.0, 09/02, page 105 of 568...
Page 142: Table 8.1 Interrupt Sources, Dtc Vector Addresses, And Corresponding Dtces
Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Origin of Source Interrupt Source Vector Number Vector Address DTCE* Priority  Software Write to DTVECR DTVECR H′0400 + (vector High number × 2) External pin IRQ0 H′0420 DTCEA7 IRQ1 H′0422 DTCEA6...
Page 143: Operation
Interrupt Origin of Source Interrupt Source Vector Number Vector Address DTCE* Priority 8-bit timer CMIA_1 H′0480 DTCED3 High channel 0 H′0482 DTCED2 8-bit timer CMIB_1 H′0488 DTCED1 channel 1 H′048A DTCED0 Reserved H′0490 DTCEE7 H′0492 DTCEE6 H′0494 DTCEE5 H′0496 DTCEE4 RXI_0 H′04A2 DTCEE3...
Page 144: Figure 8.4 Flowchart Of Dtc Operation
The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Start Read DTC vector Next transfer Read register information Data transfer...
Page 145: Normal Mode
8.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 8.2 lists the register information in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested.
Page 146: Repeat Mode
8.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 8.3 lists the register information in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Page 147: Block Transfer Mode
8.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 8.4 lists the register information in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
Page 148: Chain Transfer
8.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.8 shows the outline of the chain transfer operation.
Page 149: Interrupts
8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Page 150: Number Of Dtc Execution States
φ DTC activation request request Data transfer Vector read Read Write Read Write Address Transfer Transfer information read information write Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) φ DTC activation request request Data transfer Data transfer Vector read...
Page 151: Table 8.5 Dtc Execution Status
Table 8.5 DTC Execution Status Register Information Internal Vector Read Read/Write Data Read Data Write Operations Mode Normal Repeat Block transfer Legend N: Block size (initial setting of CRAH and CRAL) Table 8.6 Number of States Required for Each Execution Status Chip Chip On-Chip I/O...
Page 152: Procedures For Using Dtc
Procedures for Using DTC 8.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3.
Page 153: Chain Transfer
3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts.
Page 154: Software Activation
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU.
Page 155: On-Chip Ram
8.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. 8.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.
Page 156 Rev. 1.0, 09/02, page 120 of 568...
Page 157: Section 9 I/O Ports
Section 9 I/O Ports Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
Page 158: Table 9.1 Port Functions
Table 9.1 Port Functions Port and Input/Output and Port Description Other Functions Name Output Type Port 1 P17/PO15/TIOCB2/TCLKD General I/O port also functioning as TPU_2, P16/PO14/TIOCA2/IRQ1 TPU_1, and TPU_0 I/O P15/PO13/TIOCB1/TCLKC pins, PPG output pins, and interrupt input pins P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0...
Page 159 Port and Input/Output and Port Description Other Functions Name Output Type Port 9 P97/AN15 General input port also functioning as A/D P96/AN14 converter analog inputs P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port A PA3/SCK2 Built-in input pull-up MOS General I/O port also functioning as SCI_2 I/O PA2/RxD2 Push-pull or open-drain output...
Page 160 Port and Input/Output and Port Description Other Functions Name Output Type Port D Built-in input pull-up MOS General I/O port φ Port F PF7/ General I/O port also functioning as interrupt input pins, an A/D converter start trigger input pin, and a system clock output pin (φ) PF3/ADTRG/IRQ3 PF0/IRQ2...
Page 161: Port 1
Port 1 Port 1 is an 8-bit I/O port and has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 register (PORT1) 9.1.1 Port 1 Data Direction Register (P1DDR) P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1.
Page 162: Port 1 Data Register (P1Dr)
9.1.2 Port 1 Data Register (P1DR) P1DR is an 8-bit readable/writable register that stores output data for port 1 pins. Bit Name Initial Value Description P17DR Output data for a pin is stored when the pin is specified as a general purpose I/O port. P16DR P15DR P14DR...
Page 163: Pin Functions
9.1.4 Pin Functions Port 1 pins also function as TPU I/O pins, PPG output pins, and interrupt input pins. The correspondence between the register specification and the pin functions is shown below. Table 9.2 P17 Pin Function TPU Channel 2 Setting* Output Input or Initial Value ...
Page 164: Table 9.5 P14 Pin Function
Table 9.5 P14 Pin Function TPU Channel 1 Setting* Output Input or Initial Value  P14DDR   NDER12 Pin function TIOCA1 output P14 input P14 output PO12 output TIOCA1 input IRQ0 input Note:* For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Page 165: Port 3
Table 9.8 P11 Pin Function TPU Channel 0 Setting* Output Input or Initial Value  P11DDR   NDER9 Pin function TIOCB0 output P11 input P11 output PO9 output TIOCB0 input Note:* For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Page 166: Port 3 Data Register (P3Dr)
Bit Name Initial Value Description P37DDR When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the corresponding P36DDR port 3 pin an output pin. Clearing this bit to 0 makes P35DDR the pin an input pin. P34DDR P33DDR P32DDR...
Page 167: Port 3 Open-Drain Control Register (P3Odr)
Bit Name Initial Value Description Undefined* If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is Undefined* performed while P3DDR bits are cleared to 0, the pin Undefined* states are read.
Page 168: Table 9.11 P36 Pin Function
Table 9.11 P36 Pin Function P36DDR Pin function P36 input P36 output Table 9.12 P35 Pin Function P35DDR Pin function P35 input P35 output IRQ5 input* Table 9.13 P34 Pin Function P34DDR Pin function P34 input P34 output Table 9.14 P33 Pin Function P33DDR Pin function P33 input...
Page 169: Port 4
Table 9.17 P30 Pin Function TE in SCR_0  P30DDR Pin function P30 input P30 output TxD0 output Note:* When used as an external interrupt input pin, do not use as an I/O pin for another function. Port 4 Port 4 is an input-only port. Port 4 pins also function as A/D converter analog input pins. Port 4 has the following register.
Page 170: Port 7 Data Direction Register (P7Ddr)
9.4.1 Port 7 Data Direction Register (P7DDR) P7DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 7. P7DDR cannot be read, if it is, an undefined value will be read. Bit Name Initial Value Description...
Page 171: Pin Functions
Bit Name Initial Value Description Undefined* If a port 7 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 7 read is Undefined* performed while P7DDR bits are cleared to 0, the pin Undefined* states are read.
Page 172: Port 9
Table 9.22 P73 Pin Function All 0 Any of 1 OSC3 to OSC0 in TCSR_1  P73DDR Pin function P73 input P73 output TMO1 output Table 9.23 P72 Pin Function All 0 Any of 1 OSC3 to OSC0 in TCSR_0 ...
Page 173 Bit Name Initial Value Description Undefined* The pin states are always read when a port 9 read is performed. Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Note:* Determined by the states of pins P97 to P90. Rev. 1.0, 09/02, page 137 of 568...
Page 174: Port A
Port A Port A is a 4-bit I/O port that also has other functions. Port A has the following registers. • Port A data direction register (PADDR) • Port A data register (PADR) • Port A register (PORTA) • Port A pull-up MOS control register (PAPCR) •...
Page 175: Port A Data Register (Padr)
9.6.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores output data for port A pins. Bit Name Initial Value Description   7 to Undefined Reserved These bits are read as an undefined value and cannot be modified.
Page 176: Port A Pull-Up Mos Control Register (Papcr)
9.6.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR is an 8-bit register that controls the input pull-up MOS function. Bit Name Initial Value Description   7 to Undefined Reserved These bits are read as an undefined value and cannot be modified.
Page 177: Pin Functions
9.6.6 Pin Functions Port A pins also function as SCI_2 I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 9.26 PA3 Pin Function CKE1 in SCR_2  C/A in SMR_2   CKE0 in SCR_2 ...
Page 178: Port B
Port B Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. • Port B data direction register (PBDDR) • Port B data register (PBDR) • Port B register (PORTB) • Port B pull-up MOS control register (PBPCR) •...
Page 179: Port B Data Register (Pbdr)
9.7.2 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores output data for the port B pins. Bit Name Initial Value Description PB7DR Output data for a pin is stored when the pin is specified as a general purpose I/O port. PB6DR PB5DR PB4DR...
Page 180: Port B Pull-Up Mos Control Register (Pbpcr)
9.7.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR is an 8-bit readable/writable register that controls the on/off state of input pull-up MOS of port B. Bit Name Initial Value Description PB7PCR When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS PB6PCR for that pin.
Page 181: Pin Functions
9.7.6 Pin Functions Port B pins also function as TPU I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 9.30 PB7 Pin Function TPU channel 5 setting* Output Input or Initial Value  PB7DDR Pin function TIOCB5 output...
Page 182: Port C
Table 9.34 PB3 Pin Function TPU channel 3 setting* Output Input or Initial Value  PB3DDR Pin function TIOCD3 output PB3 input PB3 output TIOCD3 input Note:* For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Page 183: Port C Data Direction Register (Pcddr)
• Port C data register (PCDR) • Port C register (PORTC) • Port C pull-up MOS control register (PCPCR) • Port C open-drain control register (PCODR) 9.8.1 Port C Data Direction Register (PCDDR) PCDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port C are used for input or output.
Page 184: Port C Register (Portc)
9.8.3 Port C Register (PORTC) PORTC is an 8-bit read-only register that shows port C pin states. Bit Name Initial Value Description If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read.
Page 185: Pin Functions
Bit Name Initial Value Description PC7ODR When a pin is specified as an output port, setting the corresponding bit to 1 specifies pin output as open- PC6ODR drain and the input pull-up MOS to the off state. PC5ODR Clearing this bit to 0 specifies push-pull output. PC4ODR PC3ODR PC2ODR...
Page 186: Table 9.40 Pc5 Pin Function
Table 9.40 PC5 Pin Function BIDE        PC5DDR Pin function SSI1 SSI1 input output output input output input output input input output Table 9.41 PC4 Pin Function  BIDE      PC4DDR ...
Page 187: Table 9.44 Pc1 Pin Function
Table 9.44 PC1 Pin Function BIDE        PC1DDR Pin function SSI0 SSI0 input output output input output input output input input output Table 9.45 PC 0Pin Function  BIDE      PC0DDR ...
Page 188: Port D
Port D Port D is an 8-bit I/O port that also functions as the realtime input port pins. The realtime input port stores the pin states of port D in PDRTIDR using the IRQ3 pin as the trigger input. The falling, rising, or both edges of the IRQ3 pin can be used as a trigger timing. Port D has the following registers.
Page 189: Port D Data Register (Pddr)
9.9.2 Port D Data Register (PDDR) PDDR is an 8-bit readable/writable register that stores output data for the port D pins. Bit Name Initial Value Description PD7DR Output data for a pin is stored when the pin is specified as a general purpose I/O port. PD6DR PD5DR PD4DR...
Page 190: Port D Realtime Input Data Register (Pdrtidr)
Bit Name Initial Value Description PD7PCR When the pin is in its input state, the input pull-up MOS of the input pin is on when the corresponding PD6PCR bit is set to 1. PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR 9.9.5 Port D RealTime Input Data Register (PDRTIDR) The realtime input port stores the pin states of port D in PDRTIDR using the IRQ3 pin as the trigger input.
Page 191: Port F Data Direction Register (Pfddr)
9.10.1 Port F Data Direction Register (PFDDR) PFDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port F are used for input or output. Bit Name Initial Value Description PF7DDR When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the PF7 pin a φ...
Page 192: Port F Data Register (Pfdr)
9.10.2 Port F Data Register (PFDR) PFDR is an 8-bit readable/writable register that stores output data for the port F pins. Bit Name Initial Value Description  Reserved The write value should always be 0. PF6DR Output data for a pin is stored when the pin is specified as a general purpose I/O port.
Page 193: Pin Functions
9.10.4 Pin Functions Port F is an 8-bit I/O port. Port F pins also function as external interrupt input, IRQ2 and IRQ3, A/D trigger input (ADTRG), and system clock output (φ). Table 9.46 PF7 Pin Function PF7DDR φ output Pin function PF7 input Table 9.47 PF6 Pin Function PF6DDR...
Page 194: Table 9.52 Pf1 Pin Function
Table 9.52 PF1 Pin Function PF1DDR Pin function PF1 input PF1 output Table 9.53 PF0 Pin Function PF0DDR Pin function PF0 input PF0 output IRQ2 input* Note:* When used as an external interrupt input pin, do not use as an I/O pin for another function. Rev.
Page 195: Section 10 16-Bit Timer Pulse Unit (Tpu)
Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively.
Page 196: Table 10.1 Tpu Functions
Table 10.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 φ/1 φ/1 φ/1 φ/1 φ/1 φ/1 Count clock φ/4 φ/4 φ/4 φ/4 φ/4 φ/4 φ/16 φ/16 φ/16 φ/16 φ/16 φ/16 φ/64 φ/64 φ/64 φ/64 φ/64 φ/64...
Page 197 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture input capture input capture TGRA_0...
Page 198: Figure 10.1 Block Diagram Of Tpu
Interrupt request signals Channel 3: TGIA_3 Input/output pins TGIB_3 Channel 3: TIOCA3 TGIC_3 TIOCB3 TGID_3 TIOCC3 TCIV_3 TIOCD3 Channel 4: TGIA_4 Channel 4: TIOCA4 TGIB_4 TIOCB4 TCIV_4 Channel 5: TIOCA5 TCIU_4 TIOCB5 Channel 5: TGIA_5 TGIB_5 TCIV_5 TCIU_5 Clock input φ/1 Internal clock: φ/4...
Page 199: Input/Output Pins
10.2 Input/Output Pins Table 10.2 TPU Pins Channel Symbol Function TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin...
Page 200: Register Descriptions
10.3 Register Descriptions The TPU has the following registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. • Timer control register_0 (TCR_0) •...
Page 201 • Timer status register_3 (TSR_3) • Timer counter_3 (TCNT_3) • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) • Timer control register_4 (TCR_4) • Timer mode register_4 (TMDR_4) •...
Page 202: Timer Control Register (Tcr)
10.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel (channel 0 to 5). TCR register settings should be conducted only when TCNT operation is stopped. Bit Name Initial value Description...
Page 203: Table 10.3 Cclr0 To Cclr2 (Channels 0 And 3)
Table 10.3 CCLR0 to CCLR2 (Channels 0 and 3) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* TCNT clearing disabled...
Page 204: Table 10.5 Tpsc0 To Tpsc2 (Channel 0)
Table 10.5 TPSC0 to TPSC2 (Channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 205: Table 10.7 Tpsc0 To Tpsc2 (Channels 2)
Table 10.7 TPSC0 to TPSC2 (Channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024...
Page 206: Table 10.9 Tpsc0 To Tpsc2 (Channel 4)
Table 10.9 TPSC0 to TPSC2 (Channel 4) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Counts on TCNT5 overflow/underflow...
Page 207: Timer Mode Register (Tmdr)
10.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped. Bit Name Initial value Description...
Page 208: Table 10.11 Md0 To Md3
Table 10.11 MD0 to MD3 Bit 3 Bit 2 Bit 1 Bit 0 MD3* MD2* Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ...
Page 209: Timer I/O Control Register (Tior)
10.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required as TIOR is affected by the TMDR setting.
Page 210: Table 10.12 Tiorh_0 (Channel 0)
Table 10.12 TIORH_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 211: Table 10.13 Tiorl_0 (Channel 0)
Table 10.13 TIORL_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 212: Table 10.14 Tior_1 (Channel 1)
Table 10.14 TIOR_1 (Channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 213: Table 10.15 Tior_2 (Channel 2)
Table 10.15 TIOR_2 (Channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 214: Table 10.16 Tiorh_3 (Channel 3)
Table 10.16 TIORH_3 (Channel 3) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_3 IOB3 IOB2 IOB1 IOB0 Function TIOCB3 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 215: Table 10.17 Tiorl_3 (Channel 3)
Table 10.17 TIORL_3 (Channel 3) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_3 IOD3 IOD2 IOD1 IOD0 Function TIOCD3 Pin Function Output Output disabled compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 216: Table 10.18 Tior_4 (Channel 4)
Table 10.18 TIOR_4 (Channel 4) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_4 IOB3 IOB2 IOB1 IOB0 Function TIOCB4 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 217: Table 10.19 Tior_5 (Channel 5)
Table 10.19 TIOR_5 (Channel 5) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_5 IOB3 IOB2 IOB1 IOB0 Function TIOCB5 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 218: Table 10.20 Tiorh_0 (Channel 0)
Table 10.20 TIORH_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 219: Table 10.21 Tiorl_0 (Channel 0)
Table 10.21 TIORL_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCC0 Pin Function Output Output disabled compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 220: Table 10.22 Tior_1 (Channel 1)
Table 10.22 TIOR_1 (Channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 221: Table 10.23 Tior_2 (Channel 2)
Table 10.23 TIOR_2 (Channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 222: Table 10.24 Tiorh_3 (Channel 3)
Table 10.24 TIORH_3 (Channel 3) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_3 IOA3 IOA2 IOA1 IOA0 Function TIOCA3 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 223: Table 10.25 Tiorl_3 (Channel 3)
Table 10.25 TIORL_3 (Channel 3) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3 IOC3 IOC2 IOC1 IOC0 Function TIOCC3 Pin Function Output Output disabled compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 224: Table 10.26 Tior_4 (Channel 4)
Table 10.26 TIOR_4 (Channel 4) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_4 IOA3 IOA2 IOA1 IOA0 Function TIOCA4 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 225: Table 10.27 Tior_5 (Channel 5)
Table 10.27 TIOR_5 (Channel 5) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_5 IOA3 IOA2 IOA1 IOA0 Function TIOCA5 Pin Function Output Output disabled compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match...
Page 226: Timer Interrupt Enable Register (Tier)
10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Name Initial value Description TTGE A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare...
Page 227 Bit Name Initial value Description TGIEC TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Page 228: Timer Status Register (Tsr)
10.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Name Initial value Description TCFD Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5.
Page 229 Bit Name Initial value Description TGFD R/(W) Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. Only 0 can be written, for flag clearing. In channels 1, 2, 4, and 5, bit 3 is reserved.
Page 230 Bit Name Initial value Description TGFB R/(W) Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] When TCNT = TGRB and TGRB is functioning as •...
Page 231: Timer Counter (Tcnt)
10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H′0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Page 232: Timer Synchro Register (Tsyr)
10.3.9 Timer Synchro Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Name Initial value Description...
Page 233: Figure 10.2 Example Of Counter Operation Setting Procedure
Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of count operation setting procedure Figure 10.2 shows an example of the count operation setting procedure.
Page 234: Figure 10.3 Free-Running Counter Operation
2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H′FFFF to H′0000), the TCFV bit in TSR is set to 1.
Page 235: Figure 10.4 Periodic Counter Operation
Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 10.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 236: Figure 10.6 Example Of 0 Output/1 Output Operation
2. Examples of waveform output operation Figure 10.6 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Page 237: Figure 10.8 Example Of Input Capture Operation Setting Procedure
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Page 238: Figure 10.9 Example Of Input Capture Operation
2. Example of input capture operation Figure 10.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 239: Synchronous Operation
10.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
Page 240: Buffer Operation
Example of Synchronous Operation: Figure 10.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 241: Figure 10.12 Compare Match Buffer Operation
Table 10.28 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 TGRB_3 TGRD_3 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register.
Page 242: Figure 10.14 Example Of Buffer Operation Setting Procedure
Buffer operation Designate TGR as an input capture register or output compare register by means of TIOR. Designate TGR for buffer operation with bits BFA and BFB in TMDR. Select TGR function Set the CST bit in TSTR to 1 start the count operation.
Page 243: Figure 10.16 Example Of Buffer Operation (2)
2. When TGR is an input capture register Figure 10.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 244: Cascaded Operation
10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Page 245: Pwm Modes
TCNT_1 clock TCNT_1 H'03A1 H'03A2 TCNT_2 clock TCNT_2 H'FFFF H'0000 H'0001 TIOCA1, TIOCA2 TGRA_1 H'03A2 TGRA_2 H'0000 Figure 10.18 Example of Cascaded Operation (1) Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Page 246: Table 10.30 Pwm Output Registers And Output Pins
There are two PWM modes, as described below. • PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D.
Page 247: Figure 10.20 Example Of Pwm Mode Setting Procedure
Table 10.30 PWM Output Registers and Output Pins (cont) Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGR4A_4 TIOCA4 TIOCA4 TGR4B_4 TIOCB4 TGRA_5 TIOCA5 TIOCA5 TGRB_5 TIOCB5 Note:* In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode setting procedure.
Page 248: Figure 10.21 Example Of Pwm Mode Operation (1)
TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10.21 Example of PWM Mode Operation (1) Figure 10.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform.
Page 249: Figure 10.23 Example Of Pwm Mode Operation (3)
TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA...
Page 250: Phase Counting Mode
10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR.
Page 251: Figure 10.25 Example Of Phase Counting Mode 1 Operation
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32 summarizes the TCNT up/down-count conditions.
Page 252: Figure 10.26 Example Of Phase Counting Mode 2 Operation
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 2 Operation Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKB (Channels 1 and 5) TCLKC (Channels 2 and 4)
Page 253: Figure 10.27 Example Of Phase Counting Mode 3 Operation
3. Phase counting mode 3 Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 254: Figure 10.28 Example Of Phase Counting Mode 4 Operation
4. Phase counting mode 4 Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 255 Phase Counting Mode Application Example: Figure 10.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Page 256: Figure 10.29 Phase Counting Mode Application Example
Channel 1 Edge TCLKA TCNT_1 detection TCLKB circuit TGRA_1 (speed period capture) TGRB_1 (speed period capture) TCNT_0 TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 10.29 Phase Counting Mode Application Example Rev.
Page 257: Interrupt Sources
10.5 Interrupt Sources There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 258: Table 10.36 Tpu Interrupts
Table 10.36 TPU Interrupts Channel Name Interrupt Source Interrupt Flag Activation TGIA_0 TGRA_0 input capture/compare match TGFA_0 Possible TGIB_0 TGRB_0 input capture/compare match TGFB_0 Possible TGIC_0 TGRC_0 input capture/compare match TGFC_0 Possible TGID_0 TGRD_0 input capture/compare match TGFD_0 Possible TCIV_0 TCNT_0 overflow TCFV_0 Not possible...
Page 259: Dtc Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Page 260: Operation Timing
10.8 Operation Timing 10.8.1 Input/Output Timing TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT input clock TCNT Figure 10.30 Count Timing in Internal Clock Operation φ...
Page 261: Figure 10.32 Output Compare Output Timing
φ TCNT input clock TCNT Compare match signal TIOC pin Figure 10.32 Output Compare Output Timing Input Capture Signal Timing: Figure 10.33 shows input capture signal timing. φ Input capture input Input capture signal TCNT Figure 10.33 Input Capture Input Signal Timing Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the timing when counter clearing on compare match is specified, and figure 10.35 shows the timing when counter clearing on input capture is specified.
Page 262: Figure 10.34 Counter Clear Timing (Compare Match)
φ Compare match signal Counter clear signal H'0000 TCNT Figure 10.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal H'0000 TCNT Figure 10.35 Counter Clear Timing (Input Capture) Rev. 1.0, 09/02, page 226 of 568...
Page 263: Figure 10.36 Buffer Operation Timing (Compare Match)
Buffer Operation Timing: Figures 10.36 and 10.37 show the timing in buffer operation. φ TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 10.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 10.37 Buffer Operation Timing (Input Capture) Rev.
Page 264: Interrupt Signal Timing
10.8.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. φ TCNT input clock TCNT Compare match signal TGF flag...
Page 265: Figure 10.40 Tciv Interrupt Setting Timing
TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
Page 266: Figure 10.42 Timing For Status Flag Clearing By Cpu
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag clearing by the DTC.
Page 267: Usage Notes
10.9 Usage Notes 10.9.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 10.9.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at...
Page 268: Conflict Between Tcnt Write And Clear Operations
Where : Counter frequency φ : Operating frequency N : TGR set value 10.9.4 Conflict between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.45 shows the timing in this case.
Page 269: Conflict Between Tcnt Write And Increment Operations
10.9.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.46 shows the timing in this case. TCNT write cycle φ...
Page 270: Conflict Between Tgr Write And Compare Match
10.9.6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the previous value is written.
Page 271: Conflict Between Buffer Register Write And Compare Match
10.9.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation will be that in the buffer prior to the write. Figure 10.48 shows the timing in this case.
Page 272: Conflict Between Tgr Read And Input Capture
10.9.8 Conflict between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 10.49 shows the timing in this case. TGR read cycle φ...
Page 273: Conflict Between Tgr Write And Input Capture
10.9.9 Conflict between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.50 shows the timing in this case. TGR write cycle φ...
Page 274: 10.9.10 Conflict Between Buffer Register Write And Input Capture
10.9.10 Conflict between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.51 shows the timing in this case.
Page 275: 10.9.11 Conflict Between Overflow/Underflow And Counter Clearing
10.9.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing source, and when H′FFFF is set in TGR.
Page 276: 10.9.12 Conflict Between Tcnt Write And Overflow/Underflow
10.9.12 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation timing when there is conflict between TCNT write and overflow.
Page 277: Section 11 8-Bit Timers
Section 11 8-Bit Timers This LSI has an on-chip 8-bit timer module with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 278: Input/Output Pins
Figure 11.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1). Internal clock External clock sources sources φ/8 TMCI01 φ/64 φ/8192 Clock 1 Clock 0 Clock select TCORA_0 TCORA_1 Compare-match A1 Compare-match A0 Comparator A_0 Comparator A_1 Overflow 1 TCNT_0 TCNT_1...
Page 279: Register Descriptions
Table 11.1 Pin Configuration Channel Name Symbol Function Timer output TMO0 Output Output controlled by compare-match Timer output TMO1 Output Output controlled by compare-match Common to Timer clock input TMCI01 Input External clock input for the counter 0 and 1 Timer reset input TMRI01 Input...
Page 280: Timer Counters (Tcnt)
11.3.1 Timer Counters (TCNT) Each TCNT is an 8-bit up-counter. TCNT_0 and TCNT_1, or TCNT_2 and TCNT_3 comprise a single 16-bit register, so they can be accessed together by word access. This clock source is selected by clock select bits CKS2 to CKS0 in TCR. TCNT can be cleared by an external reset input signal or compare-match signals A and B.
Page 281 Initial Bit Name Value Description CMIEB Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled CMIEA Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA)
Page 282 Initial Bit Name Value Description CKS2 Clock Select 2 to 0 CKS1 The input clock can be selected from three clocks divided from the system clock (φ). When use of an CKS0 external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges.
Page 283: Timer Control/Status Registers (Tcsr)
11.3.5 Timer Control/Status Registers (TCSR) TCSR indicates status flags and controls compare-match output. • TCSR_0 Initial Bit Name Value Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When TCNT = TCORB [Clearing condition] • Read CMFB when CMFB = 1, then write 0 in CMFB.
Page 284 Initial Bit Name Value Description Output Select 3 and 2 These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT. 00: No change when compare-match B occurs 01: 0 is output when compare-match B occurs 10: 1 is output when compare-match B occurs 11: Output is inverted when compare-match B occurs (toggle output)
Page 285 • TCSR_1 and TCSR_3 Initial Bit Name Value Description CMFB R/(W)* Compare-Match Flag B [Setting condition] When TCNT = TCORB [Clearing condition] • Read CMFB when CMFB = 1, then write 0 in CMFB • DTC is activated by the CMIB interrupt and the DISEL bit = 0 in MRB of DTC.
Page 286 Initial Bit Name Value Description Output Select 1 and 0 These bits specify how the timer output level is to be changed by a compare-match A of TCORA and TCNT. 00: No change when compare-match A occurs 01: 0 is output when compare-match A occurs 10: 1 is output when compare-match A occurs 11: Output is inverted when compare-match A occurs (toggle output)
Page 287: Operation
Initial Bit Name Value Description  Reserved This bit is a readable/writable bit, but the write value should always be 0. Output Select 3 and 2 These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT.
Page 288: Operation Timing
TCNT H'FF Counter clear TCORA TCORB H'00 Figure 11.2 Example of Pulse Output 11.5 Operation Timing 11.5.1 TCNT Incrementation Timing Figure 11.3 shows the TCNT count timing with internal clock source. Figure 11.4 shows the TCNT incrementation timing with external clock source. The pulse width of the external clock for incrementation at signal edge must be at least 1.5 system clock (φ) periods, and at least 2.5 states for incrementation at both edges.
Page 289: Timing Of Cmfa And Cmfb Setting When A Compare-Match Occurs
φ External clock input pin TCNT input clock TCNT N – 1 N + 1 Figure 11.4 Count Timing for External Clock Input 11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match.
Page 290: Timing Of Timer Output When A Compare-Match Occurs
11.5.3 Timing of Timer Output When a Compare-Match Occurs When a compare-match occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Figure 11.6 shows the timing when the output is set to toggle at compare- match A.
Page 291: Timing Of Overflow Flag (Ovf) Setting
φ External reset input pin Clear signal TCNT N – 1 H'00 Figure 11.8 Timing of Clearing by External Reset Input 11.5.6 Timing of Overflow Flag (OVF) Setting OVF in TCSR is set to 1 when the timer count overflows (changes from H′FF to H′00). Figure 11.9 shows the timing of this operation.
Page 292: Compare-Match Count Mode
 The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. • Counter clear specification  If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare- match occurs.
Page 293: A/D Converter Activation
Table 11.2 8-Bit Timer Interrupt Sources Interrupt Interrupt source Description Flag DTC Activation Priority CMIA0 TCORA_0 compare-match CMFA Possible High CMIB0 TCORA_0 compare-match CMFB Possible OVI0 TCNT_0 overflow Not possible CMIA1 TCORA_1 compare-match CMFA Possible CMIB1 TCORA_1 compare-match CMFB Possible OVI1 TCNT_1 overflow Not possible...
Page 294: Usage Notes
11.8 Usage Notes 11.8.1 Conflict between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 11.10 shows this operation.
Page 295: Conflict Between Tcor Write And Compare-Match
TCNT write cycle by CPU φ Address TCNT address Internal write signal TCNT input clock TCNT Counter write data Figure 11.11 Conflict between TCNT Write and Increment 11.8.3 Conflict between TCOR Write and Compare-Match During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled.
Page 296: Conflict Between Compare-Matches A And B
11.8.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 11.3.
Page 297: Table 11.4 Switching Of Internal Clock And Tcnt Operation
Table 11.4 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from low Clock before switchover to low* Clock after switchover TCNT clock TCNT N + 1 CKS bit rewrite Switching from low Clock before switchover...
Page 298: Conflict Between Interrupts And Module Stop Mode
Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high Clock before switchover to low* Clock after switchover TCNT clock TCNT N + 1 N + 2 CKS bit rewrite Switching from high φ to high TCNT input clock...
Page 299: Section 12 Programmable Pulse Generator (Ppg)
Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator provides pulse outputs using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 2 and group 3) that can operate both simultaneously and independently.
Page 300: Figure 12.1 Block Diagram Of Ppg
Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 PO13 pins, group 3 Internal PO12 PODRH NDRH data bus PO11 Pulse output PO10 pins, group 2 Pulse output pins, group 1 PODRL NDRL Pulse output pins, group 0 Legend : PPG output mode register : PPG output control register...
Page 301: Input/Output Pins
12.2 Input/Output Pins Table 12.1 summarizes the pin configuration of the PPG. Table 12.1 Pin Configuration Pin Name Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output Group 2 pulse output PO10 Output Output Output 12.3 Register Descriptions...
Page 302: Next Data Enable Registers H, L (Nderh, Nderl)
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. The corresponding DDR also needs to be set to 1 in order to enable pulse output by the PPG.
Page 303: Output Data Registers H, L (Podrh, Podrl)
12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. •...
Page 304: Next Data Registers H, L (Ndrh, Ndrl)
12.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the data for the next pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. •...
Page 305 Bit Name Initial Value Description   7 to All 1 Reserved These bits are always read as 1 and cannot be modified. NDR11 Next Data Register 8 to11 NDR10 The register contents are transferred to the corresponding PODRH bits by the output trigger NDR9 specified with PCR.
Page 306: Ppg Output Control Register (Pcr)
Bit Name Initial Value Description   7 to All 1 Reserved These bits are always read as 1 and cannot be modified. NDR3 Next Data Register 3 to 0 NDR2 The register contents are transferred to the corresponding PODRL bits by the output trigger NDR1 specified with PCR.
Page 307: Ppg Output Mode Register (Pmr)
12.3.5 PPG Output Mode Register (PMR) The PMR is an 8-bit readable/writable register that selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0.
Page 308: Operation
12.4 Operation 12.4.1 Overview Figure 12.2 shows a block diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Page 309: Output Timing
12.4.2 Output Timing If pulse output is enabled, the contents of NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
Page 310: Sample Setup Procedure For Normal Pulse Output
12.4.3 Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. Normal PPG output [1] Set TIOR to make TGRA an output compare register (with output disabled) Select TGR functions [2] Set the PPG output trigger period Set TGRA value [3] Select the counter clock source with TPU setup...
Page 311: Example Of Normal Pulse Output (Example Of Five-Phase Pulse Output)
12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)
Page 312: Non-Overlapping Pulse Output
12.4.5 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred on PODR bits on compare match A. • On compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1.
Page 313: Figure 12.7 Non-Overlapping Operation And Ndr Write Timing
Compare match A Compare match B Write to NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR Write to NDR here here Do not write Do not write to NDR here to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Rev.
Page 314: Sample Setup Procedure For Non-Overlapping Pulse Output
12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping [1] Set TIOR to make TGRA and PPG output TGRB an output compare registers (with output disabled) Select TGR functions [2] Set the pulse output trigger period in TGRB and the non-overlap Set TGR values...
Page 315: Example Of Non-Overlapping Pulse Output (Example Of Four-Phase Complementary Non-Overlapping Output)
12.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary non- overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13...
Page 316 1. Set up the TPU channel to be used as the output trigger channel such that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared on compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
Page 317: Inverted Pulse Output
12.4.8 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9.
Page 318: Pulse Output Triggered By Input Capture
12.4.9 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 319: Section 13 Watchdog Timer
Section 13 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer.
Page 320: Register Descriptions
13.2 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different method to normal registers. For details, refer to section 13.5.1, Notes on Register Access. •...
Page 321 Bit Name Initial Value Description Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H′00.   All 1 Reserved These bits are always read as 1 and cannot be modified.
Page 322: Reset Control/Status Register (Rstcsr)
13.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H′1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows.
Page 323: Operation
13.3 Operation 13.3.1 Watchdog Timer Mode Operation To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H′00) before overflow occurs.
Page 324: Interrupts
13.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 13.1 WDT Interrupt Source Name Interrupt Source...
Page 325: Conflict Between Timer Counter (Tcnt) Write And Increment
TCNT write Writing to RSTE and RSTS bits Address: H'FF74 H'5A Write data H'FF76 TCSR write Writing 0 to WOVF bit Address: H'FF74 H'5A Write data or H'00 H'FF76 Figure 13.3 Writing to TCNT, TCSR, and RSTCSR (example for WDT0) Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as other registers.
Page 326: Changing Value Of Cks2 To Cks0
13.5.3 Changing Value of CKS2 to CKS0 If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS0 to CKS2.
Page 327: Section 14 Serial Communication Interface (Sci)
Section 14 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Page 328: Figure 14.1 Block Diagram Of Sci
Clocked Synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors detected Smart Card Interface • Automatic transmission of error signal (parity error) in receive mode • Error signal detection and automatic data retransmission in transmit mode •...
Page 329: Input/Output Pins
14.2 Input/Output Pins Table 14.1 shows the serial pins for each SCI channel. Table 14.1 Pin Configuration Channel Pin Name* Function SCK0 SCI0 clock input/output RxD0 Input SCI0 receive data input TxD0 Output SCI0 transmit data output SCK2 SCI2 clock input/output RxD2 Input SCI2 receive data input...
Page 330: Receive Shift Register (Rsr)
14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 331: Serial Mode Register (Smr)
14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source. Some bit functions of SMR differ between normal serial communication interface mode and Smart Card interface mode. •...
Page 332 Bit Name Initial Value Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. CKS1 Clock Select 0 and 1: CKS0 These bits select the clock source for the baud rate generator.
Page 333 • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Name Initial Value Description GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of one bit), and clock output control mode addition is performed.
Page 334 Bit Name Initial Value Description CKS1 Clock Select 0 and 1 CKS0 These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.9, Bit...
Page 335: Serial Control Register (Scr)
14.3.6 Serial Control Register (SCR) SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, refer to section 14.8, Interrupt Sources. Some bit functions of SCR differ between normal serial communication interface mode and Smart Card interface mode.
Page 336 Bit Name Initial Value Description CKE1 Clock Enable 0 and 1 CKE0 Selects the clock source and SCK pin function. Asynchronous mode 00: Internal baud rate generator SCK pin functions as I/O port 01: Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK pin.
Page 337 • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled.
Page 338: Serial Status Register (Ssr)
14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ between normal serial communication interface mode and Smart Card interface mode.
Page 339 Bit Name Initial Value Description ORER Overrun Error [Setting condition] • When the next serial reception is completed while RDRF = 1 [Clearing condition] • When 0 is written to ORER after reading ORER = 1 Framing Error [Setting condition] •...
Page 340 Bit Name Initial Value Description Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. MPBT Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit data.
Page 341 Bit Name Initial Value Description ORER Overrun Error [Setting condition] • When the next serial reception is completed while RDRF = 1 [Clearing condition] • When 0 is written to ORER after reading ORER = 1 Error Signal Status [Setting condition] •...
Page 342 Bit Name Initial Value Description TEND Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] •...
Page 343: Smart Card Mode Register (Scmr)
14.3.8 Smart Card Mode Register (SCMR) SCMR is a register that selects Smart Card interface mode and its format. Bit Name Initial Value Description   7 to All 1 Reserved These bits are always read as 1. SDIR Smart Card Data Transfer Direction Selects the serial/parallel conversion format.
Page 344: Bit Rate Register (Brr)
14.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 14.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
Page 345: Table 14.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ φ φ φ (MHz) 4.9152 Bit Rate (bit/s) Error (%) Error (%) Error (%) 0.03 0.31 –0.25 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00...
Page 346: Table 14.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ φ φ φ (MHz) 9.8304 12.288 Bit Rate Error Error Error Error (bit/s) –0.26 –0.25 0.03 0.08 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00...
Page 347: Table 14.3 Brr Settings For Various Bit Rates (Asynchronous Mode) (3)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ φ φ φ (MHz) 19.6608 Bit Rate Error Error Error Error (bit/s) –0.12 0.31 –0.25 –0.44 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16 1200...
Page 348: Table 14.5 Maximum Bit Rate With External Clock Input (Asynchronous Mode)
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) External Input Maximum Bit External Input Maximum Bit φ φ φ φ (MHz) φ φ φ φ (MHz) Clock (MHz) Rate (bit/s) Clock (MHz) Rate (bit/s) 1.0000 62500 3.0000 187500 4.9152 1.2288...
Page 349: Table 14.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ φ φ φ (MHz) Bit Rate (bit/s)                 2.5k 100k 250k 500k ...
Page 350: Table 14.8 Examples Of Bit Rate For Various Brr Settings (Smart Card Interface Mode) (When N = 0 And S = 372)
Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372) Operating Frequency φ φ φ φ (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate Error Error Error Error (bit/s) 9600 0.00 8.99...
Page 351: Operation In Asynchronous Mode
14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Page 352: Table 14.10 Serial Transfer Formats (Asynchronous Mode)
Table 14.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP...
Page 353: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 354: Clock
14.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Page 355: Sci Initialization (Asynchronous Mode)
14.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Page 356: Data Transmission (Asynchronous Mode)
14.4.5 Data Transmission (Asynchronous Mode) Figure 14.6 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 357: Figure 14.7 Sample Serial Transmission Flowchart
[1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 358: Serial Data Reception (Asynchronous Mode)
14.4.6 Serial Data Reception (Asynchronous Mode) Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 359: Table 14.11 Ssr Status Flags And Receive Data Handling
Table 14.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception.
Page 360: Figure 14.9 Sample Serial Reception Data Flowchart (1)
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 361: Figure 14.9 Sample Serial Reception Data Flowchart (2)
Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 14.9 Sample Serial Reception Data Flowchart (2) Rev.
Page 362: Multiprocessor Communication Function
14.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Page 363: Figure 14.10 Example Of Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to...
Page 364: Multiprocessor Serial Data Transmission
14.5.1 Multiprocessor Serial Data Transmission Figure 14.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Page 365: Multiprocessor Serial Data Reception
14.5.2 Multiprocessor Serial Data Reception Figure 14.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 366: Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. Read MPIE bit in SCR [3] SCI status check, ID reception and Read ORER and FER flags in SSR comparison: Read SSR and check that the RDRF...
Page 367: Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)
Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 368: Operation In Clocked Synchronous Mode
14.6 Operation in Clocked Synchronous Mode Figure 14.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Page 369: Sci Initialization (Clocked Synchronous Mode)
14.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 14.15. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 370: Serial Data Transmission (Clocked Synchronous Mode)
14.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 14.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 371: Figure 14.17 Sample Serial Transmission Flowchart
[1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin. [2] SCI status check and transmit data Read TDRE flag in SSR write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Page 372: Serial Data Reception (Clocked Synchronous Mode)
14.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR.
Page 373: Figure 14.19 Sample Serial Reception Flowchart
[1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 374: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after initializing the SCI. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Page 375: Figure 14.20 Sample Flowchart Of Simultaneous Serial Transmit And Receive Operations
[1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data Start transmission/reception input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE...
Page 376: Operation In Smart Card Interface
14.7 Operation in Smart Card Interface The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting.
Page 377: Data Format (Except For Block Transfer Mode)
14.7.2 Data Format (Except for Block Transfer Mode) Figure 14.22 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
Page 378: Block Transfer Mode
With the direction convention type IC and the above sample start character, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H′3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0.
Page 379: Receive Data Sampling Timing And Reception Margin In Smart Card Interface Mode
14.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0.
Page 380: Initialization
14.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3.
Page 381: Figure 14.26 Retransfer Operation In Sci Transmit Mode
Figure 14.28 shows a flowchart for transmission. The sequence of transmit operations can be performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1.
Page 382: Figure 14.27 Tend Flag Generation Timing In Transmission Operation
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 14.27. I/O data Guard time (TEND interrupt) 12.5etu When GM = 0 11.0etu When GM = 1 Legend : Start bit : Data bits...
Page 383: Figure 14.28 Example Of Transmission Processing Flow
Start Initialization Start transmission ERS = 0? Error processing TEND = 1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted ? ERS = 0? Error processing TEND = 1? Clear TE bit to 0 Figure 14.28 Example of Transmission Processing Flow Rev.
Page 384: Serial Data Reception (Except For Block Transfer Mode)
14.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 14.29 illustrates the retransfer operation when the SCI is in receive mode. 1.
Page 385: Clock Output Control
Start Initialization Start reception ORER = 0 and PER = 0 Error processing RDRF = 1? Read RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit to 0 Figure 14.30 Example of Reception Processing Flow 14.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and...
Page 386: Figure 14.32 Clock Halt And Restart Procedure
When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure clock duty cycle from power-on, the following switching procedure should be followed.
Page 387: Interrupt Sources
14.8 Interrupt Sources 14.8.1 Interrupts in Normal Serial Communication Interface Mode Table 14.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Page 388: Interrupts In Smart Card Interface Mode
14.8.2 Interrupts in Smart Card Interface Mode Table 14.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 14.13 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag DTC Activation ERI_0 Receive Error, error...
Page 389: Usage Notes
14.9 Usage Notes 14.9.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes.
Page 390 Rev. 1.0, 09/02, page 354 of 568...
Page 391: Section 15 Hitachi Controller Area Network (Hcan)
Section 15 Hitachi Controller Area Network (HCAN) The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. For details on CAN specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH.
Page 392: Figure 15.1 Hcan Block Diagram
• Other features  DTC can be activated by message reception mailbox (HCAN mailbox 0 only) • Module stop mode can be set HCAN (CDLC) Message buffer Mailboxes Data Link Controller Message control Bosch CAN 2.0B active LAFM Message data MC0–MC15, MD0–MD15 HTxD Tx buffer...
Page 393: Input/Output Pins
15.2 Input/Output Pins Table 15.1 shows the HCAN’s pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 15.1 HCAN Pins Name Abbreviation Input/Output Function HCAN transmit data pin HTxD Output CAN bus transmission pin...
Page 394: Master Control Register (Mcr)
• HCAN Monitor Register (HCANMON) 15.3.1 Master Control Register (MCR) MCR is an 8-bit register that controls the HCAN. Bit Name Initial Value Description MCR7 HCAN Sleep Mode Release When this bit is set to 1, the HCAN automatically exits HCAN sleep mode on detection of CAN bus operation.
Page 395: General Status Register (Gsr)
Bit Name Initial Value Description MCR0 Reset Request When this bit is set to 1, the HCAN transits to reset mode. For details, refer to section 15.4.1, Hardware and Software Resets. [Setting conditions] • Power-on reset • Hardware standby • Software standby •...
Page 396 Bit Name Initial Value Description GSR2 Message Transmission Status Flag Flag that indicates whether the module is currently in the message transmission period. This bit cannot be modified. [Setting condition] • Start of message transmission (SOF) [Clearing condition] • Interval of three bits after EOF (End of Frame) GSR1 Transmit/Receive Warning Flag This bit cannot be modified.
Page 397: Bit Configuration Register (Bcr)
15.3.3 Bit Configuration Register (BCR) BCR is a 16-bit register that is used to set HCAN bit timing parameters and the baud rate prescaler. For details on parameters, refer to section 15.4.2, Initialization after Hardware Reset. Bit Name Initial Value Description BCR7 Re-Synchronization Jump Width (SJW)
Page 398 Bit Name Initial Value Description BCR11 Time Segment 1 (TSEG1) BCR10 Set the TSEG1 (PRSEG + PHSEG1) width to between 4 and 16 time quanta. BCR9 0000: Setting prohibited BCR8 0001: Setting prohibited 0010: Setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta...
Page 399: Mailbox Configuration Register (Mbcr)
15.3.4 Mailbox Configuration Register (MBCR) MBCR is a 16-bit register that is used to set the transfer direction for each mailbox. Bit Name Initial Value Description MBCR7 These bits set the transfer direction for the corresponding mailboxes 1 to 15. MBCRn MBCR6 determines the transfer direction for mailbox n (n MBCR5...
Page 400: Transmit Wait Register (Txpr)
15.3.5 Transmit Wait Register (TXPR) TXPR is a 16-bit register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). Bit Name Initial Value Description TXPR7 These bits set a transmit wait (CAN bus arbitration wait) for the corresponding mailboxes 1 to 15.
Page 401: Transmit Wait Cancel Register (Txcr)
15.3.6 Transmit Wait Cancel Register (TXCR) TXCR is a 16-bit register that controls the cancellation of transmit wait messages in mailboxes (buffers). Bit Name Initial Value Description TXCR7 These bits cancel the transmit wait message in the corresponding mailboxes 1 to 15. When TXCRn (n TXCR6 = 1 to 15) is set to 1, the transmit wait message in TXCR5...
Page 402: Transmit Acknowledge Register (Txack)
15.3.7 Transmit Acknowledge Register (TXACK) TXACK is a 16-bit register containing status flags that indicate the normal transmission of mailbox (buffer) transmit messages. Bit Name Initial Value Description TXACK7 R/(W)* These bits are status flags that indicate error-free transmission of the transmit message in the TXACK6 R/(W)* corresponding mailboxes 1 to 15.
Page 403: Abort Acknowledge Register (Aback)
15.3.8 Abort Acknowledge Register (ABACK) ABACK is a 16-bit register containing status flags that indicate the normal cancellation (aborting) of mailbox (buffer) transmit messages. Bit Name Initial Value Description ABACK7 R/(W)* These bits are status flags that indicate error-free cancellation (abortion) of the transmit message in ABACK6 R/(W)* the corresponding mailboxes 1 to 15.
Page 404: Receive Complete Register (Rxpr)
15.3.9 Receive Complete Register (RXPR) RXPR is a 16-bit register containing status flags that indicate the normal reception of messages in mailboxes (buffers). For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (RFPR) bit is also set to 1 simultaneously.
Page 405: Remote Request Register (Rfpr)
15.3.10 Remote Request Register (RFPR) RFPR is a 16-bit register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set to 1, the corresponding receive complete register (RXPR) bit is also set to 1 simultaneously. Bit Name Initial Value Description...
Page 406: Interrupt Register (Irr)
15.3.11 Interrupt Register (IRR) IRR is a 16-bit interrupt status flag register. Bit Name Initial Value Description IRR7 R/(W)* Overload Frame [Setting condition] • When an overload frame is transmitted in error active/passive state [Clearing condition] • Writing 1 IRR6 R/(W)* Bus Off Interrupt Flag Status flag indicating the bus off state caused by...
Page 407 Bit Name Initial Value Description IRR4 R/(W)* Receive Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the receive error counter. [Setting condition] When REC ≥ 96 [Clearing condition] • Writing 1 IRR3 R/(W)* Transmit Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the transmit error counter.
Page 408 Bit Name Initial Value Description IRR0 R/(W)* Reset Interrupt Flag Status flag indicating that the HCAN module has been reset. This bit cannot be masked by the interrupt mask register (IMR). If this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts.
Page 409 Bit Name Initial Value Description IRR9 Unread Interrupt Flag Status flag indicating that a receive message has been overwritten before being read. [Setting condition] • When UMSR (unread message status register) is set [Clearing condition] • Clearing of all bits in UMSR (unread message status register) IRR8 R/(W)*...
Page 410: Mailbox Interrupt Mask Register (Mbimr)
15.3.12 Mailbox Interrupt Mask Register (MBIMR) MBIMR is a 16-bit register that controls the enabling or disabling of individual mailbox (buffer) interrupt requests. Bit Name Initial Value Description MBIMR7 Mailbox Interrupt Mask (MBIMRx) MBIMR6 When MBIMRn (n = 1 to 15) is cleared to 0, the interrupt request in mailbox n is enabled.
Page 411: Interrupt Mask Register (Imr)
15.3.13 Interrupt Mask Register (IMR) IMR is a 16-bit register containing flags that enable or disable requests by individual interrupt sources. The reset interrupt flag cannot be masked. Bit Name Initial Value Description IMR7 Overload Frame Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR7 (OVR0) is enabled.
Page 412: Receive Error Counter (Rec)
Bit Name Initial Value Description IMR12 Bus Operation Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR12 (OVR0) is enabled. When set to 1, it is masked.  3, 2 All 1 Reserved These bits are always read as 1. The write value should always be 0.
Page 413: Unread Message Status Register (Umsr)
15.3.16 Unread Message Status Register (UMSR) UMSR is a 16-bit register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. When overwritten by a new message, data in the unread receive message is lost. Bit Name Initial Value Description...
Page 414: Local Acceptance Filter Masks (Lafml, Lafmh)
15.3.17 Local Acceptance Filter Masks (LAFML, LAFMH) LAFML and LAFMH are 16-bit registers that individually set the identifier bits of the message to be stored in mailbox 0 as Don’t Care. For details, refer to section 15.4.4, Message Reception. The relationship between the identifier bits and mask bits are shown in the following.
Page 415 LAFMH Bit Name Initial Value Description LAFMH7 When this bit is set to 1, ID-20 of the receive message identifier is not compared. LAFMH6 When this bit is set to 1, ID-19 of the receive message identifier is not compared. LAFMH5 When this bit is set to 1, ID-18 of the receive message identifier is not compared.
Page 416: Message Control (Mc0 To Mc15)
15.3.18 Message Control (MC0 to MC15) The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message control registers are in RAM, their initial values after power-on are undefined. Be sure to initialize them by writing 0 or 1. Figure 15.2 shows the register names for each mailbox.
Page 417 Register Name Bit Name Description  MCx[1] 7 to 4 The initial value of these bits is undefined. They must be initialized by writing 0 or 1. 3 to 0 DLC3 to Data Length Code DLC0 Set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits.
Page 418: Message Data (Md0 To Md15)
15.3.19 Message Data (MD0 to MD15) The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message data registers are in RAM, their initial values after power- on are undefined. Be sure to initialize them by writing 0 or 1. Figure 15.5 shows the register names for each mailbox.
Page 419 Bit Name Initial Value Description RxDIE HRxD Interrupt Enable Selects whether an IRQ2 interrupt is caused by PF0 or HRxD pin. 0: An IRQ2 interrupt is caused by pin PF0 1: An IRQ2 interrupt is caused by the HRxD pin TxSTP HTxD Transmission Stop Controls transmission stop of the HTxD pin.
Page 420: Operation
15.4 Operation 15.4.1 Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. • Hardware Reset At power-on reset, or in hardware or software standby mode, the HCAN is initialized by automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR.
Page 421: Figure 15.6 Hardware Reset Flowchart
Hardware reset : Settings by user : Processing by hardware MCR0 = 1 (automatic) IRR0 = 1 (automatic) GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Clear IRR0 Period in which BCR, MBCR, etc., BCR setting are initialized MBCR setting Mailbox initialization Message transmission method initialization...
Page 422: Figure 15.7 Software Reset Flowchart
MCR0 = 1 : Settings by user Bus idle? : Processing by hardware GSR3 = 1 (automatic) Initialization of REC and TEC only Correction BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? Correction IMR setting MBIMR setting...
Page 423: Figure 15.8 Detailed Description Of One Bit
1-bit time (8–25 time quanta) SYNC_SEG PRSEG PHSEG1 PHSEG2 Time segment 2 Time segment 1 (TSEG1) (TSEG2) 1 time quanta 2–16 time quanta Figure 15.8 Detailed Description of One Bit SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal bit edge transitions occur in this segment.
Page 424: Table 15.3 Setting Range For Tseg1 And Tseg2 In Bcr
Time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. f is the system clock frequency. tq = 2 × (BPR setting + 1)/f The following formula is used to calculate the 1-bit time and bit rate. 1-bit time = tq ×...
Page 425 Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding mailbox for reception use. When setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages should be set in low-to-high mailbox order.
Page 426: Message Transmission
15.4.3 Message Transmission Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 15.9. Initialization (after hardware reset only) : Settings by user Clear IRR0 BCR setting : Processing by hardware MBCR setting...
Page 427 CPU interrupt source settings: The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR). Arbitration field setting: The arbitration field is set by the message control registers MCx[5] to MCx[8] in a transmit mailbox.
Page 428: Figure 15.10 Transmit Message Cancellation Flowchart
interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: •...
Page 429: Message Reception
15.4.4 Message Reception The reception procedure after initial settings is described below. A reception flowchart is shown in Figure 15.11. Initialization : Settings by user Clear IRR0 BCR setting : Processing by hardware MBCR setting Mailbox (RAM) initialization Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings...
Page 430 CPU interrupt source settings: CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also specified. Data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the MBIMR.
Page 431 or more mailbox of the mailboxes 1 to 15. On receiving a message, a CPU interrupt request may be generated according to the settings of the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). • Remote frame reception A mailbox can store two kinds of messages: data frames and remote frames.
Page 432: Hcan Sleep Mode
: Settings by user Unread message overwrite : Processing by hardware UMSR = 1 IRR9 = 1 IMR9 = 1? Interrupt to CPU Clear IRR9 Message control/message data read Figure 15.12 Unread Message Overwrite Flowchart 15.4.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current consumption.
Page 433: Figure 15.13 Hcan Sleep Mode Flowchart
MCR5 = 1 : Settings by user : Processing by hardware Bus idle? Initialize TEC and REC Bus operation? IRR12 = 1 IMR12 = 1? CPU interrupt No (automatic) Sleep mode clearing method MCR7 = 0? Yes (manual) Clear sleep mode? MCR5 = 0 MCR5 = 0 11 recessive bits...
Page 434 HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected: •...
Page 435: Hcan Halt Mode
15.4.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 15.14 shows a flowchart of the HCAN halt mode. MCR1 = 1 Bus idle? Set MBCR MCR1 = 0 : Settings by user...
Page 436: Interrupt Sources
15.5 Interrupt Sources Table 15.4 lists the HCAN interrupt sources. These sources can be masked except the reset processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER). For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller.
Page 437: Dtc Interface
15.6 DTC Interface The DTC can be activated by the reception of a message in HCAN mailbox 0. When the DTC activation is set and DTC transfer ends, the RXPR0 and RFPR0 flags are automatically cleared. An interrupt request is not sent to the CPU by a reception interrupt from the HCAN. Figure 15.15 shows a DTC transfer flowchart.
Page 438: Can Bus Interface
15.7 CAN Bus Interface A bus transceiver IC is necessary to connect the H8S/2628 Series to a CAN bus. A Philips PCA82C250 transceiver IC is recommended. If any other product is used, confirm that it is compatible with the PCA82C250. Figure 15.16 shows a sample connection diagram.
Page 439: Hcan Sleep Mode
15.8.3 HCAN Sleep Mode The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set even in sleep mode.
Page 440: 15.8.10 Hcan Txcr Operation
15.8.10 HCAN TXCR Operation When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR) may not be cleared even if transmission is canceled. This occurs when the following conditions are all satisfied.
Page 441: Section 16 Synchronous Serial Communication Unit (Ssu)
Section 16 Synchronous Serial Communication Unit (SSU) This LSI has two independent synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication.
Page 442: Figure 16.1 Block Diagram Of Ssu
Figure 16.1 shows a block diagram of the SSU. Module data bus Internal data bus SSCRH SSCRL SSTDR 0 SSRDR 0 SSMR SSTDR 1 SSRDR 1 SSER SSTDR 2 SSRDR 2 SSSR SSTDR 3 SSRDR 3 Control circuit φ Clock φ/2 SSTRSR φ/4...
Page 443: Input/Output Pins
16.2 Input/Output Pins Table 16.1 shows the SSU pin configuration. Table 16.1 Pin Configuration Name Symbol Function SSU clock SSCK SSU clock input/output SSU receive data input SSU receive data input/output SSU transmit data output SSU transmit data input/output SSU chip select input/output SSU chip select input/output 16.3 Register Descriptions...
Page 444 Bit Name Initial Value Description BIDE Bidirectional Mode Enable Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 16.5.3, Relationship between Data I/O Pins and Shift Register.
Page 445: Ss Control Register L (Sscrl)
Bit Name Initial Value Description SCS Pin Selection CSS1 Select that the SCS pin functions as a port or SCS CSS0 input or output. However, when MSS = 0, the SCS pin functions as an input pin regardless of the CSS1 and CSS0 settings.
Page 446: Ss Mode Register (Ssmr)
16.3.3 SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock phase, clock polarity, and clock rate of synchronous serial communication. Bit Name Initial Value Description MSB First/LSB First Selects the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first CPOS...
Page 447: Ss Enable Register (Sser)
16.3.4 SS Enable Register (SSER) SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit Name Initial Value Description Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. ...
Page 448: Ss Status Register (Sssr)
16.3.5 SS Status Register (SSSR) SSSR is a status flag register for interrupts. Bit Name Initial Value Description   Reserved The write value should always be 0. ORER Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination.
Page 449 Bit Name Initial Value Description TDRE Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] • When the TE bit in SSER is 0 • When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. [Clearing conditions] •...
Page 450 Bit Name Initial Value Description Conflict/Incomplete Error Indicates that a conflict error has occurred when 0 is externally input via the SCS pin with MSS = 1. If the SCS pin level changes to 1 during slave operation, an incomplete error occurs because it is determined that a master device has terminated the transfer.
Page 451: Ss Transmit Data Register 0 To 3 (Sstdr0 To Sstdr3)
16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid.
Page 452: Operation
16.4 Operation 16.4.1 Transfer Clock A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set SCKS in SSCRH to 1 to select the SSCK pin as a serial clock. When MSS in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin.
Page 453: Data Transmission And Data Reception
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 16.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 16.3 (2)).
Page 454: Figure 16.4 Example Of Ssu Initialization
Start initialization [1] Specify master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Clear TE and RE bits in SSER to 0 [2] Specify transmit/receive data length. Specify CSS1, CSS0, MSS, BIDE, SOL, [3] Specify MSB first/LSB first selection, clock and SCKS bits polarity selection, clock phase selection,...
Page 455: Figure 16.5 Example Of Transmission Operation
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame 1 frame SSCK SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) TDRE TEND LSI operation interrupt interrupt interrupt interrupt User operation generated generated generated...
Page 456: Figure 16.6 Example Of Data Transmission Flowchart
Start [1] Initialization: Specify the settings such as transmit data format. Initialization TE = 1 (transmission enabled) [2] Check tha SSU state and write transmit data: Write transmit data to SSTDR after Read TDRE in SSR reading and confirming that the TDRE bit is 1.
Page 457 When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped.
Page 458: Figure 16.7 Example Of Reception Operation
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS 0 1 frame 1 frame SSCK SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) RDRF LSI operation interrupt interrupt User operation generated generated Dummy-read Read SSRDR0 SSRDR0 (2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS 0...
Page 459: Figure 16.8 Example Of Data Reception Flowchart
Start Initialization: Specify the settings such as receive data format. Initialization Start reception: When SSRDR is dummy-read with RE = 1, RE = 1 (reception enabled) reception is started. [3], [6] Receive error processing: Dummy-read SSRDR When a receive error occurs execute the designated error processing after reading the ORER bit in SSSR.
Page 460: Scs Pin Control And Arbitration
[1] Initialization: Start Specify the settings such as transmit/receive data format Initialization [2] Check the SSU state and write transmit data: Transmission/reception started Write transmit data to SSTDR after reading (TE = 1, RE = 1) and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to Read TDRE in SSSR.
Page 461: Interrupt Requests
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0 before resuming the transmission or reception. External input to Internal-clocked Transfer start Data written to SSTDR Hi-Z output Arbitration detection Worst time for period internally clocking SCS...
Page 462: Usage Note
The TDRE, TEND, and RDRF bits are automatically cleared to 0 by the DTC data transfer. Since these interrupt requests are allocated to four vector addresses: SSEr_i0, SSRx_i0, SSTx_i0 and SSERT_i1, the interrupt sources must be distinguished by flags. Table 16.2 lists interrupt sources. Table 16.2 Interrupt Souses Channel Abbreviation...
Page 463: Section 17 A/D Converter
Section 17 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. The block diagram of the A/D converter is shown in figure 17.1. 17.1 Features • 10-bit resolution •...
Page 464: Figure 17.1 Block Diagram Of A/D Converter
Module data bus Internal data bus 10-bit D/A φ/2 φ/4 Comparator Control circuit φ/8 φ/16 Sample-and- hold circuit interrupt AN10 Conversion start AN11 trigger from TPU AN12 AN13 AN14 AN15 Legend ADCR : A/D control register ADDRB : A/D data register B ADCSR : A/D control/status register ADDRC : A/D data register C ADDRA : A/D data register A...
Page 465: Input/Output Pins
17.2 Input/Output Pins Table 17.1 summarizes the input pins used by the A/D converter. 16 analog input pins are divided into four groups, each of which includes four channels; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1, analog input pins 8 to 11 (AN8 to AN11) comprising group 2, and analog input pins 12 to 15 (AN12 to AN15) comprising group 3.
Page 466: Register Description
17.3 Register Description The A/D converter has the following registers. Module stop mode for the A/D converter is specified with the MSTPA1 bit in the module stop control register (MSTPCRA). For details on the module stop control register A (MSTPCRA), refer to section 21.1.2, Module Stop Control Register A to C (MSTPCRA to MSTPCRC).
Page 467: A/D Control/Status Register (Adcsr)
17.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Name Initial Value Description R/(W) A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends • When A/D conversion ends on all specified channels [Clearing conditions] •...
Page 468 Bit Name Initial Value Description SCAN Scan Mode Selects the A/D conversion operating mode. 0: Single mode 1: Scan mode Channel Select 0 to 3 Select analog input channels. When SCAN = 0 When SCAN = 1 0000: AN0 0000: AN0 0001: AN1 0001: AN0, AN1 0010: AN2...
Page 469: A/D Control Register (Adcr)
17.3.3 A/D Control Register (ADCR) The ADCR enables A/D conversion started by an external trigger signal. Bit Name Initial Value Description TRGS1 Timer Trigger Select 0 and 1 TRGS0 Enable the start of A/D conversion by a trigger signal. Bits TRGS0 and TRGS1 should be set while A/D conversion is stopped (ADST = 0).
Page 470: Operation
17.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, clear the ADST bit in ADCSR to 0 first in order to prevent incorrect operation. The ADST bit can be set at the same time as the operating mode or analog input channel is changed.
Page 471: Input Sampling And A/D Conversion Time
17.4.3 Input Sampling and A/D Conversion Time The A/D converter includes the sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) has passed after the ADST bit is set to 1, and then conversion is started.
Page 472: Table 17.3 A/D Conversion Time (Single Mode)
Table 17.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max  ...
Page 473: External Trigger Input Timing
17.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When bits TRGS0 and TRGS1 in ADCR are set to 11, an external trigger is input on the ADTRG pin. At the falling edge of the ADTRG pin, the ADST bit in ADCSR is set to 1, and the A/D conversion starts.
Page 474: A/D Conversion Accuracy Definitions
17.6 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.4). •...
Page 475: Figure 17.4 A/D Conversion Accuracy Definitions
Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 17.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 17.5 A/D Conversion Accuracy Definitions Rev.
Page 476: Usage Notes
17.7 Usage Notes 17.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode.
Page 477: Range Of Analog Power Supply And Other Pin Settings
17.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤...
Page 478: Figure 17.7 Example Of Analog Input Protection Circuit
AVCC AN0 to AN15 0.1 F AVSS Notes: Values are reference values. 10 F 0.01 F 2. R : Input impedance Figure 17.7 Example of Analog Input Protection Circuit Table 17.6 Analog Pin Specifications Item Unit  Analog input capacitance ...
Page 479: Section 18 Ram
Section 18 RAM The H8S/2628 has 8 kbytes, and the H8S/2627 has 6 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data.
Page 480 Rev. 1.0, 09/02, page 444 of 568...
Page 481: Section 19 Rom
Section 19 ROM The features of the flash memory are summarized below. The block diagram of the flash memory is shown in figure 19.1. 19.1 Features • Size: 128 kbytes • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 482: Mode Transitions
Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller mode Mode pins EBR1 EBR2 RAMER Flash memory (128 kbytes) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2: Erase block register 2 RAMER:...
Page 483: Figure 19.2 Flash Memory State Transitions
MD1 = 1, MD2 = 1, Reset state FWE = 0 User mode (on-chip ROM enabled) MD1 = 1, MD2 = 1, FWE = 1 MD2 = 0 MD1 = 1, FWE = 1 FWE = 0 FWE = 1 Programmer mode User...
Page 484: Figure 19.3 Boot Mode
1. Initial state 2. Programming control program transfer When boot mode is entered, the boot program in The old program version or data remains written in the flash memory. The user should prepare the this LSI (originally incorporated in the chip) is programming control program and new started and the programming control program in application program beforehand in the host.
Page 485: Figure 19.4 User Program Mode
1. Initial state 2. Programming/erase control program transfer The FWE assessment program that confirms that When user program mode is entered, user user program mode has been entered, and the software confirms this fact, executes transfer program that will transfer the programming/erase program in the flash memory, and transfers the control program from flash memory to on-chip programming/erase control program to RAM.
Page 486: Block Configuration
19.3 Block Configuration Figure 19.5 shows the block configuration of 128-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 32 kbytes (2 blocks), 28 kbytes (1 block), 16 kbytes (1 block), 8 kbytes (2 blocks), and 1 kbyte (4 blocks).
Page 487: Input/Output Pins
19.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 19.2. Table 19.2 Pin Configuration Pin Name Function Input Reset Input Flash program/erase protection by hardware Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode TxD2...
Page 488: Flash Memory Control Register 1 (Flmcr1)
19.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 makes the flash memory enter program mode, program-verify mode, erase mode, or erase-verify mode. For details on the register setting, refer to section 19.8, Flash Memory Programming/Erasing. Bit Name Initial Value Description —...
Page 489: Flash Memory Control Register 2 (Flmcr2)
19.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 indicates the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Name Initial Value Description FLER Indicates that an error has occurred during flash memory programming or erasing.
Page 490: Erase Block Register 2 (Ebr2)
19.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR1 is initialized to H′00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, otherwise, all the bits in EBR1 are be automatically cleared to 0.
Page 491: On-Board Programming Modes
Bit Name Initial Value Description RAM2 Flash Memory Area Selection RAM1 Specifies one of the following flash memory areas RAM0 to overlap the RAM area of H′FFE000 to H′FFE3FF when the RAMS bit is set to 1. The areas correspond with 1-kbyte erase blocks. 00X: H′000000 to H′0003FF (EB0) 01X: H′000400 to H′0007FF (EB1) 10X: H′000800 to H′000BFF (EB2)
Page 492: Boot Mode
19.6.1 Boot Mode Table 19.4 shows the boot mode operations from a reset end to a branch to the programming control program. 1. In boot mode, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 19.8, Flash Memory Programming/Erasing.
Page 493: Table 19.4 Boot Mode Operation
Table 19.4 Boot Mode Operation Host Operation LSI Operation Processing Contents Processing Contents Item Communications Contents Boot mode Branches to boot program at reset-start. start Boot program initiation Bit rate Continuously transmits data H'00 at H'00, H'00 ..H'00 · Measures low-level period of receive data adjustment specified bit rate.
Page 494: Programming/Erasing In User Program Mode
19.6.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory.
Page 495: Flash Memory Emulation In Ram
19.7 Flash Memory Emulation in RAM A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 496: Figure 19.8 Example Of Ram Overlap Operation
An example in which flash memory block area EB0 is overlapped is shown in figure 19.8. 1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range H′FFE000 to H′FFE3FF. 2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area of the EB0 to EB3 blocks.
Page 497: Flash Memory Programming/Erasing
19.8 Flash Memory Programming/Erasing The flash memory is programmed or erased in on-board programming mode by a software method using the CPU. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode perform programming/erasing in combination with these modes.
Page 498: Figure 19.9 Program/Program-Verify Flowchart
Start of programming Write pulse application subroutine Perform programming in the erased state. Apply Write Pulse START Do not perform additional programming on previously programmed addresses. Set SWE bit in FLMCR1 WDT enable ) µs Wait (t sswe Set PSU1 bit in FLMCR1 Store 128-byte program data in program ) µs data area and reprogram data area...
Page 499: Erase/Erase-Verify
19.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.10 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Specify a single block o be erased with the erase block registers (EBR1 and EBR2).
Page 500: Figure 19.10 Erase/Erase-Verify Flowchart
Erase start SWE bit ← 1 Wait 1 µs n ← 1 Set EBR1 and EBR2 Enable WDT ESU1 bit ← 1 Wait 100 µs E1 bit ← 1 Wait 10 µs E1 bit ← 0 Wait 10 µs ESU1 bit ← 0 Wait 10 µs Disable WDT EV1 bit ←...
Page 501: Program/Erase Protection
19.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 19.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized.
Page 502: Programmer Mode
• Standby mode All flash memory circuits are halted. Table 19.6 shows the correspondence between the operating modes of the H8S/2628 Series and the flash memory. When the flash memory returns to its normal operating state from standby mode, a period to settle the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 µs, even when the external clock is being used.
Page 503: Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block diagram of the clock pulse generator is shown in figure 20.1.
Page 504: Register Descriptions
20.1 Register Descriptions The on-chip clock pulse generator has the following registers. • System clock control register (SCKCR) • Low-power control register (LPWRCR) 20.1.1 System Clock Control Register (SCKCR) SCKCR performs φ clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control.
Page 505: Low-Power Control Register (Lpwrcr)
Bit Name Initial Value Description SCK2 System Clock Select 0 to 2 SCK1 These bits select the bus master clock. SCK0 000: High-speed mode 001: Medium-speed clock is φ/2 010: Medium-speed clock is φ/4 011: Medium-speed clock is φ/8 100: Medium-speed clock is φ/16 101: Medium-speed clock is φ/32 11X: Setting prohibited Legend...
Page 506: Oscillator
20.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 20 MHz. 20.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20.2.
Page 507: External Clock Input
20.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When complementary clock is input to the XTAL pin, the external clock input should be fixed high in standby mode.
Page 508: Figure 20.5 External Clock Input Timing
Table 20.3 shows the input conditions for the external clock. Table 20.3 External Clock Input Conditions = 5.0 V ± ± ± ± 10% Item Symbol Unit Test Conditions  External clock input low 20.8 Figure 20.5 pulse width  External clock input high 20.8 pulse width...
Page 509: Pll Circuit
20.3 PLL Circuit The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set by the STC0 bit and the STC1 bit in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
Page 510: Usage Notes
20.6 Usage Notes 20.6.1 Note on Crystal Resonator As various characteristics related to the crystal resonator are closely linked to the user’s board design, thorough evaluation is necessary on the user’s part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer.
Page 511: Figure 20.7 External Circuitry Recommended For Pll Circuit
R1 : 3 k C1 : 470 pF PLLCAP PLLV CB : 0.1 F* CB : 0.1 F (Values are preliminary recommended values.) Note:* CB is laminated ceramic. Figure 20.7 External Circuitry Recommended for PLL Circuit Rev. 1.0, 09/02, page 475 of 568...
Page 512 Rev. 1.0, 09/02, page 476 of 568...
Page 513: Section 21 Power-Down Modes
Section 21 Power-Down Modes In addition to the normal program execution state, this LSI has five power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
Page 514: Figure 21.1 Mode Transition Diagram
Program-halted state pin = Low Hardware Reset state standby mode pin = High pin = Low pin = High Program execution state SSBY = 0 Sleep mode SLEEP command (main clock) High-speed mode (main clock) Any interrupt * SLEEP SCK2 to SCK2 to SSBY = 1 command...
Page 515: Table 21.2 Lsi Internal States In Each Mode
Table 21.2 LSI Internal States in Each Mode Medium- Module Software Hardware Function High-Speed Sleep Speed Stop Standby Standby System clock pulse Operate Operate Operate Operate Halted Halted generator Instructions Operate Medium- Halted High/ Halted Halted Registers speed (retained) medium- (retained) (undefined) operation...
Page 516: Register Descriptions
21.1 Register Descriptions Registers related to the power down mode are shown below. For details on the system clock control register (SCKCR), refer to section 20.1.1, System Clock Control Register (SCKCR). • System clock control register (SCKCR) • Standby control register (SBYCR) •...
Page 517 Bit Name Initial Value Description STS2 Standby Timer Select 0 to 2 STS1 These bits select the MCU wait time for clock settling when software standby mode is cancelled STS0 by an external interrupt. With a crystal oscillator (Table 21.3), select a wait time of 8ms (oscillation settling time) or more, depending on the operating frequency.
Page 518: Module Stop Control Registers A To C (Mstpcra To Mstpcrc)
21.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC) MSTPCR is comprised of three 8-bit readable/writable registers, and performs module stop mode control. Setting a bit to 1 causes the corresponding module to enter module stop mode. Clearing the bit to 0 clears the module stop mode.
Page 519: Medium-Speed Mode
MSTPC7* MSTPC6* MSTPC5* MSTPC4 PC break controller (PBC) MSTPC3 Hitachi Controller Area Network (HCAN) MSTPC2 Synchronous serial communication unit (SSU) MSTPC1* MSTPC0* Note:* MSTPA7 is a readable/writable bit with an initial value of 0. The write value should always be 0.
Page 520: Sleep Mode
Figure 21.2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode φ, peripheral module clock Bus master clock SCKCR Internal address bus SCKCR Internal write signal Figure 21.2 Medium-Speed Mode Transition and Clearance Timing 21.3 Sleep Mode 21.3.1 Transition to Sleep Mode If SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the sleep mode.
Page 521: Software Standby Mode
21.4 Software Standby Mode 21.4.1 Transition to Software Standby Mode A transition is made to software standby mode if the SLEEP instruction is executed when the SBYCR SSBY bit is set to 1. In this mode, the CPU, on-chip peripheral modules, and oscillator, all stop.
Page 522: Setting Oscillation Stabilization Time After Clearing Software Standby Mode
21.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. • Using a Crystal Oscillator: Set bits STS0 to STS2 so that the standby time is at least 8 ms (the oscillation settling time). Table 21.3 shows the standby times for different operating frequencies and settings of bits STS0 to STS2.
Page 523: Software Standby Mode Application Example
21.4.4 Software Standby Mode Application Example Figure 21.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
Page 524: Hardware Standby Mode
21.5 Hardware Standby Mode 21.5.1 Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption.
Page 525: Module Stop Mode
Timing of Recovery from Hardware Standby Mode Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a power-on reset. t≥100ns OSC1 Figure 21.5 Timing of Recovery from Hardware Standby Mode 21.6 Module Stop Mode 21.6.1 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules.
Page 526: Clock Output Disabling Function
φ φ φ φ Clock Output Disabling Function 21.7 The output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ...
Page 527: Writing To Mstpcr
21.8.5 Writing to MSTPCR MSTPCR should only be written to by the CPU. Rev. 1.0, 09/02, page 491 of 568...
Page 528 Rev. 1.0, 09/02, page 492 of 568...
Page 529: Section 22 List Of Registers
Section 22 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) •...
Page 530: Register Addresses (Address Order)
22.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Number Data Access of Bits Width State Register Name...
Page 531 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message control 1[2] MC1[2] H′F829 HCAN Message control 1[3] MC1[3] H′F82A HCAN Message control 1[4] MC1[4] H′F82B HCAN Message control 1[5] MC1[5] H′F82C HCAN Message control 1[6] MC1[6] H′F82D HCAN Message control 1[7]...
Page 532 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message control 5[3] MC5[3] H′F84A HCAN Message control 5[4] MC5[4] H′F84B HCAN Message control 5[5] MC5[5] H′F84C HCAN Message control 5[6] MC5[6] H′F84D HCAN Message control 5[7] MC5[7] H′F84E HCAN Message control 5[8]...
Page 533 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message control 9[4] MC9[4] H′F86B HCAN Message control 9[5] MC9[5] H′F86C HCAN Message control 9[6] MC9[6] H′F86D HCAN Message control 9[7] MC9[7] H′F86E HCAN Message control 9[8] MC9[8] H′F86F HCAN Message control 10[1]...
Page 534 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message control 13[5] MC13[5] H′F88C HCAN Message control 13[6] MC13[6] H′F88D HCAN Message control 13[7] MC13[7] H′F88E HCAN Message control 13[8] MC13[8] H′F88F HCAN Message control 14[1] MC14[1] H′F890 HCAN Message control 14[2]...
Page 535 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message data 1[6] MD1[6] H′F8BD HCAN Message data 1[7] MD1[7] H′F8BE HCAN Message data 1[8] MD1[8] H′F8BF HCAN Message data 2[1] MD2[1] H′F8C0 HCAN Message data 2[2] MD2[2] H′F8C1 HCAN Message data 2[3]...
Page 536 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message data 5[7] MD5[7] H′F8DE HCAN Message data 5[8] MD5[8] H′F8DF HCAN Message data 6[1] MD6[1] H′F8E0 HCAN Message data 6[2] MD6[2] H′F8E1 HCAN Message data 6[3] MD6[3] H′F8E2 HCAN Message data 6[4]...
Page 537 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message data 9[8] MD9[8] H′F8FF HCAN Message data 10[1] MD10[1] H′F900 HCAN Message data 10[2] MD10[2] H′F901 HCAN Message data 10[3] MD10[3] H′F902 HCAN Message data 10[4] MD10[4] H′F903 HCAN Message data 10[5]...
Page 538 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Message data 14[1] MD14[1] H′F920 HCAN Message data 14[2] MD14[2] H′F921 HCAN Message data 14[3] MD14[3] H′F922 HCAN Message data 14[4] MD14[4] H′F923 HCAN Message data 14[5] MD14[5] H′F924 HCAN Message data 14[6]...
Page 539 Number Data Access Register Name Abbreviation of Bits Address* Module Width State SS enable register_1 SSER_1 H′FB13 SSU_1 SS status register_1 SSSR_1 H′FB14 SSU_1 SS transmit data register 0_1 SSTDR0_1 8 H′FB16 SSU_1 SS transmit data register 1_1 SSTDR1_1 8 H′FB17 SSU_1 SS transmit data register 2_1...
Page 540 Number Data Access Register Name Abbreviation of Bits Address* Module Width State IRQ sense control register L ISCRL H′FE13 IRQ enable register H′FE14 IRQ status register H′FE15 DTC enable register A DTCERA H′FE16 DTC enable register B DTCERB H′FE17 DTC enable register C DTCERC H′FE18 DTC enable register D...
Page 541 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Port 3 open drain control register P3ODR H′FE46 PORT Port A open drain control register PAODR H′FE47 PORT Port B open drain control register PBODR H′FE48 PORT Port C open drain control register PCODR H′FE49 PORT...
Page 542 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Timer I/O control register_5 TIOR_5 H′FEA2 TPU_5 Timer interrupt enable register_5 TIER_5 H′FEA4 TPU_5 Timer status register_5 TSR_5 H′FEA5 TPU_5 Timer counter H_5 TCNTH_5 H′FEA6 TPU_5 Timer counter L_5 TCNTL_5 H′FEA7 TPU_5...
Page 543 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Timer mode register_0 TMDR_0 H′FF11 TPU_0 Timer I/O control register H_0 TIORH_0 H′FF12 TPU_0 Timer I/O control register L_0 TIORL_0 H′FF13 TPU_0 Timer interrupt enable register_0 TIER_0 H′FF14 TPU_0 Timer status register_0 TSR_0...
Page 544 Number Data Access Register Name Abbreviation of Bits Address* Module Width State Timer general register AH_2 TGRAH_2 H′FF38 TPU_2 Timer general register AL_2 TGRAL_2 H′FF39 TPU_2 Timer general register BH_2 TGRBH_2 H′FF3A TPU_2 Timer general register BL_2 TGRBL_2 H′FF3B TPU_2 Timer control register_0 TCR_0 H′FF68...
Page 545 Number Data Access Register Name Abbreviation of Bits Address* Module Width State A/D data register BH ADDRBH H′FF92 A/D data register BL ADDRBL H′FF93 A/D data register CH ADDRCH H′FF94 A/D data register CL ADDRCL H′FF95 A/D data register DH ADDRDH H′FF96 A/D data register DL...
Page 546: Register Bits
22.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row. Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 547 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 HCAN LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 LAFMH7 LAFMH6 LAFMH5  ...
Page 548 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  MC3[5] ID−20 ID−19 ID−18 ID−17 ID−16 HCAN MC3[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21 MC3[7] ID−7 ID−6 ID−5 ID−4 ID−3 ID−2...
Page 549 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MC7[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21 HCAN MC7[7] ID−7 ID−6 ID−5 ID−4 ID−3 ID−2 ID−1 ID−0 MC7[8] ID−15 ID−14 ID−13 ID−12...
Page 550 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MC11[7] ID−7 ID−6 ID−5 ID−4 ID−3 ID−2 ID−1 ID−0 HCAN MC11[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9 ID−8   ...
Page 551 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MC15[7] ID−7 ID−6 ID−5 ID−4 ID−3 ID−2 ID−1 ID−0 HCAN MC15[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9 ID−8 MD0[1] Bit 7 Bit 6 Bit 5 Bit 4...
Page 552 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MD3[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCAN MD4[1] Bit 7 Bit 6 Bit 5 Bit 4...
Page 553 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MD8[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCAN MD8[2] Bit 7 Bit 6 Bit 5 Bit 4...
Page 554 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MD12[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCAN MD12[3] Bit 7 Bit 6 Bit 5 Bit 4...
Page 555 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  SSCRH BIDE SOLP SCKS CSSI CSSO SSU_0      SSCRL SRES DATSI DATSO   SSMR CPOS CPHS CKS2 CKS1...
Page 556 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSU_1 SSTDR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...
Page 557 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module       LPWR STC1 STC0 SYSTEM         BARA BAA23 BAA22 BAA21 BAA20 BAA19...
Page 558 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR ...
Page 559 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module  TCR_4 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_4 TMDR_4     TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0...
Page 560 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module   IPRK IPR6 IPR5 IPR4 IPR2 IPR1 IPR0   IPRM IPR6 IPR5 IPR4 IPR2 IPR1 IPR0    ...
Page 561 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCNTL_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TPU_1 TGRAH_1 Bit 15 Bit 14 Bit 13 Bit 12...
Page 562 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TDR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCI_0 SSR_0*1 TDRE RDRF ORER TEND MPBT...
Page 563 Abbrevia- tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module     PORTA PORT PORTB PORTC PORTD PORTF Notes: 1. For buffer operation. 2. For free operation. 3. Normal serial communication interface mode. 4.
Page 564: Register States In Each Operating Mode
22.3 Register States in Each Operating Mode Register High Medium Module Software Hardware Abbreviation Reset Speed Speed Stop Standby Standby Sleep Module    Initialized Initialized Initialized Initialized HCAN    Initialized Initialized Initialized Initialized    Initialized Initialized Initialized...
Page 565 Register High Medium Module Software Hardware Abbreviation Reset Speed Speed Sleep Stop Standby Standby Module    MC1[6] Initialized Initialized Initialized Initialized HCAN    MC1[7] Initialized Initialized Initialized Initialized    MC1[8] Initialized Initialized Initialized Initialized ...
Page 566 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    MC5[7] Initialized Initialized Initialized Initialized HCAN    MC5[8] Initialized Initialized Initialized Initialized    MC6[1] Initialized Initialized Initialized Initialized ...
Page 567 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    MC9[8] Initialized Initialized Initialized Initialized HCAN    MC10[1] Initialized Initialized Initialized Initialized    MC10[2] Initialized Initialized Initialized Initialized ...
Page 568 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    MC14[1] Initialized Initialized Initialized Initialized HCAN    MC14[2] Initialized Initialized Initialized Initialized    MC14[3] Initialized Initialized Initialized Initialized ...
Page 569 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    MD2[2] Initialized Initialized Initialized Initialized HCAN    MD2[3] Initialized Initialized Initialized Initialized    MD2[4] Initialized Initialized Initialized Initialized ...
Page 570 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    MD6[3] Initialized Initialized Initialized Initialized HCAN    MD6[4] Initialized Initialized Initialized Initialized    MD6[5] Initialized Initialized Initialized Initialized ...
Page 571 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    MD10[4] Initialized Initialized Initialized Initialized HCAN    MD10[5] Initialized Initialized Initialized Initialized    MD10[6] Initialized Initialized Initialized Initialized ...
Page 572 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby MD14[5] Initialized Initialized Initialized Initialized HCAN    MD14[6] Initialized Initialized Initialized Initialized    MD14[7] Initialized Initialized Initialized Initialized    MD14[8] Initialized Initialized...
Page 573 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    SSTDR2_1 Initialized Initialized Initialized Initialized SSU_1    SSTDR3_1 Initialized Initialized Initialized Initialized    SSRDR0_1 Initialized Initialized Initialized Initialized ...
Page 574 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby      DTCERA Initialized Initialized      DTCERB Initialized Initialized      DTCERC Initialized Initialized  ...
Page 575 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby       PCODR Initialized PORT      TCR_3 Initialized Initialized TPU_3      TMDR_3 Initialized Initialized ...
Page 576 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby      TCNTH_5 Initialized Initialized TPU_5      TCNTL_5 Initialized Initialized      TGRAH_5 Initialized Initialized ...
Page 577 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby      TSR_0 Initialized Initialized TPU_0      TCNTH_0 Initialized Initialized      TCNTL_0 Initialized Initialized ...
Page 578 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby      TCR_0 Initialized Initialized TMR_0      TCR_1 Initialized Initialized TMR_1      TCSR_0 Initialized Initialized ...
Page 579 Register Reset High Medium Sleep Module Software Hardware Module Abbreviation Speed Speed Stop Standby Standby    ADDRDH Initialized Initialized Initialized Initialized    ADDRDL Initialized Initialized Initialized Initialized    ADCSR Initialized Initialized Initialized Initialized  ...
Page 580 Rev. 1.0, 09/02, page 544 of 568...
Page 581: Section 23 Electrical Characteristics
Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 lists the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (XTAL, EXTAL) –0.3 to V +0.3 Input voltage (port 4 and 9) –0.3 to AV +0.3 Input voltage (except XTAL,...
Page 582: Dc Characteristics
23.2 DC Characteristics Table 23.2 lists the DC characteristics. Table 23.3 lists the permissible output currents. Table 23.2 DC Characteristics Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = 0 V, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) *...
Page 583 Test Item Symbol Unit Conditions  Input pull-up Ports A to D –I µA = 0 V MOS current   Input = 0 V capacitance   f = 1 MHz   All input pins = 25°C except RES and NMI ...
Page 584: Ac Characteristics
Table 23.3 Permissible Output Currents Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = 0 V, = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) * Item Symbol Min Unit...
Page 585: Clock Timing
23.3.1 Clock Timing Table 23.4 lists the clock timing Table 23.4 Clock Timing = 0 V, φ =4MHz to 24MHz, Conditions : V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item...
Page 586: Control Signal Timing
EXTAL DEXT DEXT OSC1 OSC1 φ Figure 23.3 Oscillation Settling Timing 23.3.2 Control Signal Timing Table 23.5 lists the control signal timing. Table 23.5 Control Signal Timing = 0 V, φ =4MHz to 24MHz, Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = –20°C to +75°C (regular specifications), T...
Page 587: Figure 23.4 Reset Input Timing
φ RESS RESS RESW Figure 23.4 Reset Input Timing φ NMIS NMIH NMIW (i = 0 to 5) IRQW IRQS IRQH Edge input IRQS Level input Figure 23.5 Interrupt Input Timing Rev. 1.0, 09/02, page 551 of 568...
Page 588: Timing Of On-Chip Peripheral Modules
23.3.3 Timing of On-Chip Peripheral Modules Table 23.6 lists the timing of on-chip peripheral modules. Table 23.6 Timing of On-Chip Peripheral Modules = 0 , φ =4MHz to 24MHz, Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range...
Page 589: Table 23.7 Timing Of Ssu
Item Symbol Unit Test Conditions  Trigger input setup Figure 23.12 TRGS converter time  HCAN* Transmit data delay Figure 23.13 HTXD time  Transmit data setup HRXS time  Transmit data hold HRXH time  Pulse output delay Figure 23.14 time Note:* The HCAN input signal is asynchronous.
Page 590 Item Symbol Unit Test Conditions Clock cycle Figure 23.15 Master SUCYC Figure 23.16 Slave Figure 23.17  Clock high Master Figure 23.18  level pulse Slave width  Clock low Master  level pulse Slave width  Clock rise Master RISE ...
Page 591: Figure 23.6 I/O Port Input/Output Timing
φ Ports 1, 3, 4, 7, 9, A to D, F (read) Ports 1, 3, 7, A to D, F (write) Figure 23.6 I/O Port Input/Output Timing φ RTIPH Port D input Figure 23.7 Realtime Input Port Data Input Timing φ...
Page 592: Figure 23.9 Tpu Clock Input Timing
φ TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 23.9 TPU Clock Input Timing SCKW SCKr SCKf SCK0 to SCK2 Scyc Figure 23.10 SCK Clock Input Timing SCK0 to SCK2 TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) Figure 23.11 SCI Input/Output Timing (Clocked Synchronous Mode) φ...
Page 593: Figure 23.13 Hcan Input/Output Timing
V OL V OL φ t HTXD HTxD (transmit data) t HRXS t HRXH HRxD (receive data) Figure 23.13 HCAN Input/Output Timing φ PO15 to 8 Figure 23.14 PPG Output Timing (output) LEAD FALL RISE SSCK (output) CPOS = 1 SCS (output) CPOS = 0 SUCYC...
Page 594: Figure 23.16 Ssu Timing (Master, Cphs = 0)
SCS (output) LEAD FALL RISE SSCK (output) CPOS = 1 SCS (output) CPOS = 0 SUCYC SSO (output) SSI (input) Figure 23.16 SSU Timing (Master, CPHS = = = = 0) (input) LEAD FALL RISE SSCK (input) CPOS = 1 SCS (input) CPOS = 0 SUCYC...
Page 595: Figure 23.18 Ssu Timing (Slave, Cphs = 0)
(input) LEAD FALL RISE SSCK (input) CPOS = 1 SCS (input) CPOS = 0 SUCYC SSO (input) SSI (output) Figure 23.18 SSU Timing (Slave, CPHS = = = = 0) Rev. 1.0, 09/02, page 559 of 568...
Page 596: A/D Conversion Characteristics
23.4 A/D Conversion Characteristics Table 23.8 lists the A/D conversion characteristics. Table 23.8 A/D Conversion Characteristics = 0V, φ =4MHz to 24MHz, Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 597: Flash Memory Characteristics
23.5 Flash Memory Characteristics Table 23.9 lists the flash memory characteristics. Table 23.9 Flash Memory Characteristics Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, = PLLV = AV = 0 V, = 0 to +75°C (Programming / erasing operating temperature range) Item Symbol Min Unit...
Page 598 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. Programming time per 128 bytes (shows the total period for which the P1 bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) Block erase time (shows the total period for which the E1-bit FLMCR1 is set.
Page 599: Appendix
Appendix I/O Port States in Each Pin State Program Hardware Software Execution Operating Standby Standby State Sleep Port Name Mode Reset Mode Mode Mode Port 1 Keep I/O port Port 3 Keep I/O port Port 4 Input port Port 7 Keep I/O port Port 9...
Page 600: Product Code Lineup
Standard product HD6432628 H8S/2627 Masked ROM version Standard product HD6432627 Package Dimensions The package dimension that is shown in the Hitachi Semiconductor Package Data Book has priority. 16.0 ± 0.2 Unit: mm *0.22 ± 0.05 0.08 M 0.20 ± 0.04 0˚...
Page 601 Index 16-Bit Timer Pulse Unit (TPU) ....159 break address........85, 88 Buffer Operation......204 break conditions ........88 Cascaded Operation ......208 Bus Arbitration..........95 Free-running count operation ..198 bus cycle............93 Input Capture ........201 Bus Masters..........95 periodic count operation ....198 Clock Pulse Generator ......467 Phase Counting Mode......
Page 602 Program/Program-Verify....461 Interrupts programming units......450 ADI ..........437 Programming/Erasing in User Program CMIA..........257 Mode..........458 CMIB ..........257 General Registers........18 ERS0/OVR0........400 HCAN..........94, 355 NMI............71 11 consecutive recessive bits ... 384 OVI ..........257 Arbitration field ....... 391, 394 RM0 ..........400 buffer segment .........
Page 603 Operating Mode Selection ......47 LPWRCR ....469, 503, 521, 537 Operation Field ......... 37 MBCR...... 363, 494, 510, 528 PC Break Controller ......... 85 MBIMR....374, 494, 510, 528 Pin Arrangement......... 3 MC ......380, 494, 511, 528 PLL Circuit ..........473 MCR ......
Page 604 RDR......294, 508, 526, 542 TSR ......294, 505, 522, 539 REC ......376, 494, 510, 528 TSTR......195, 506, 523, 540 RFPR ....... 369, 494, 510, 528 TSYR ....... 196, 506, 523, 540 RSR ..........294 TXACK....366, 494, 510, 528 RSTCSR ....
Page 605 H8S/2628 Series Hardware Manual Publication Date: 1st. Edition, September 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.

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Hd64f2628 Hd6432628 H8s/2627 Hd6432627

Hitachi H8S/2628 Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 PC Break Controller (PBC)

Section 7 Bus Controller

Section 8 Data Transfer Controller (DTC)

Section 9 I/O Ports

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