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9.2
Register Descriptions
9.2.1
Standby Control Register (SBYCR)
Bit
:
SSBY
Initial value
:
R/W
:
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1, Standby
Control Register (SBYCR). SBYCR is initialized to H'00 by a reset.
Bits 1 and 0 System Clock Select 1 and 0 (SCK1, SCK0): These bits select the bus master
clock for high-speed mode and medium-speed mode.
Bit 1
Bit 0
SCK1
SCK0
0
0
1
1
0
1
Rev. 1.0, 02/00, page 174 of 1141
7
6
STS2
0
0
R/W
R/W
Description
Bus master is in high-speed mode
Medium-speed clock is φ/16
Medium-speed clock is φ/32
Medium-speed clock is φ/64
5
4
STS1
STS0
0
0
R/W
R/W
3
2
—
—
SCK1
0
0
—
—
R/W
1
0
SCK0
0
0
R/W
(Initial value)
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