Hitachi H8S/2199 Hardware Manual page 747

Single-chip microcomputer

Table of Contents

Sync Signal Control Register (SYNCR)

Initial value :

Note: * Only 0 can be written

SYNCR is an 8-bit register that controls the noise detection, field detection, polarity of the sync

signal input, etc.

It is initialized to H'F8 by a reset, or in stand-by mode. Bits 7 to 4 are reserved. No write is valid.

Bit 1 is read-only.

Bits 7 to 4    Reserved: Cannot be modified and are always read as 1.

Bit 3    Interrupt Selection Bit (NIS/VD): Selects whether an interrupt request is generated by

noise level detection or VD signal detection.

Interrupt at the noise level

Interrupt at VD

Bit 2    Noise Detection Flag (NOIS): NOIS is a status flag indicating that the noise counts

reached at more than four times of the value set in NDR. The flag is cleared only by writing 0

after reading 1. Care is required because it is not cleared automatically.

Noise count is smaller than four times of the value set in NDR

Noise count is the same or greater than four times of the value set in NDR

Rev. 1.0, 02/00, page 741 of 1141

(Initial value)