Interrupt Control Registers A To D (Icra To Icrd) - Hitachi H8S/2199 Hardware Manual

6.2.2

Interrupt Control Registers A to D (ICRA to ICRD)

Bit :
ICR7
Initial value :
R/W
R/W :
The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for
interrupts other than NMI.
The correspondence between ICR settings and interrupt sources is shown in table 6.3.
The ICR registers are initialized to H'00 by a reset.
Bits 7 to 0    Interrupt Control Level (ICR7 to ICR0): Set the control level for the
corresponding interrupt source.
Bit n
ICRn Description
0 Corresponding interrupt source is control level 0 (non-priority)
1 Corresponding interrupt source is control level 1 (priority)
Table 6.3 Correspondence between Interrupt Sources and ICR Settings
ICRA ICRA7
Reserved
ICRB ICRB7
Data slicer Sync
ICRC ICRC7
Timer X1
ICRD ICRD7
HSW2
7 6
ICR6 ICR5
0 0
R/W R/W
ICRA6 ICRA5
Input HSW1
capture
ICRB6 ICRB5
Servo
separator (drum,
capstan
latch)
ICRC6 ICRC5
Synchro- Watchdog
nized timer
detection
ICRD6 ICRD5
Reserved Reserved
5 4
ICR4 ICR3
0 0
R/W R/W
ICRA4 ICRA3
IRQ0 IRQ1
ICRB4 ICRB3
Timer A Timer B
ICRC4 ICRC3
Servo IIC
ICRD4 ICRD3
Reserved Reserved
3 2
ICR2 ICR1
0 0
R/W R/W
ICRA2 ICRA1
IRQ2 IRQ4
IRQ3 IRQ5
ICRB2 ICRB1
Timer J Timer R
ICRC2 ICRC1
SCI1 IIC0
(UART)
ICRD2 ICRD1
Reserved Reserved
Rev. 1.0, 02/00, page 101 of 1141
1 0
ICR0
0 0
R/W
(Initial value)
(n = 7 to 0)
CIRA0
Sync
separator,
OSD
ICRB0
Timer L
ICRC0
A/D
ICRD0
Reserved