Hitachi H8S/2199 Hardware Manual page 270

Bit 5    Enabling Interrupt of the Timer B (TMBIE): This bit works to permit/prohibit
occurrence of interrupt of timer B when the TCB overflows and when the TMBIF is set to 1.
Bit 5
TMBIE Description
0 Prohibits interrupt of timer B
1 Permits interrupt of timer B
Bits 4 and 3    Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0    Clock Selection (TMB12 to TMB10): These bits work to select the clock to input to
the TCB. Selection of the rising edge or the falling edge is workable with the external event
inputs.
Bit 2 Bit 1
TMB12 TMB11
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: * The edge selection for the external event inputs is made by setting the PMRA6 of the
port mode register A (PMRA). See section 12.2.4, Port Mode Register A (PMRA).
Rev. 1.0, 02/00, page 256 of 1141
Bit 0
TMB10 Descriptions
Internal clock: Counts at φ/16384
0
Internal clock: Counts at φ/4096
1
Internal clock: Counts at φ/1024
0
Internal clock: Counts at φ/512
1
Internal clock: Counts at φ/128
0
Internal clock: Counts at φ/32
1
Internal clock: Counts at φ/8
0
1 Counts at the rising edge and the falling edge of external
event inputs (TMBI) *
(Initial value)
(Initial value)