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21.3
Noise Cancel Circuit
The ,& pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such
as remote control receiving. The noise cancel circuit samples the input values of the ,& pin twice
at an interval of 256 states. If the input values are different, they are assumed to be noise.
The ,& pin can specify enable/disable of the noise cancel function according to the bit 4
(NCon/off) of the prescalar unit control/status register (PCSR).
21.4
Operation
21.4.1
Prescalar S (PSS)
The PSS is a 17-bit counter that uses the system clock (φ=fosc) as an input clock and generates the
frequency division clocks (φ/131072 to φ/2) of the peripheral function. The low-order 17 bits of
the 18-bit free running counter (FRC) correspond to the PSS. The FRC is incremented by one
clock. The PSS output is shared by the timer and serial communication interface (SCI), and the
frequency division ratio can independently be set by each built-in peripheral function.
When reset, the FRC is initialized to H'00000, and starts increment after reset has been released.
Because the system clock oscillator is stopped in standby mode, watch mode, subactive mode, and
subsleep mode, the PSS operation is also stopped. In this case, the FCR is also initialized to
H'00000.
The FRC cannot be read and written from the CPU.
Rev. 1.0, 02/00, page 394 of 1141
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