Hitachi H8S/2199 Hardware Manual page 757

Servo Interrupt Enable Register 2 (SIENR2)
Bit :
Initial value :
R/W :
SIENR2 is an 8-bit read/write register that enables or disables interrupts in the servo section. It is
initialized to H'FC by a reset, stand-by or module stop.
Bits 7 to 2    Reserved: Cannot be modified and are always read as 1.
Bit 1    Vertical Sync Signal Interrupt Enable Bit (IESNC)
Bit 1
IESNC Description
0 Disables the request of the interrupt (interrupt to the vertical sync signal) by
IRRSNC
1 Enables the request of the interrupt by IRRSNC
Bit 0    CTL Interrupt Enable Bit (IECTL)
Bit 0
IECTL Description
0 Disables the request of the interrupt by IRRCTL
1 Enables the request of the interrupt by IRRCTL
7 6
— —
1 1
— —
5 4
— —
1 1
— —
3 2
— —
IESNC
1 1
— —
R/W
Rev. 1.0, 02/00, page 751 of 1141
1 0
IECTL
0 0
R/W
(Initial value)
(Initial value)