Hitachi H8S/2199 Hardware Manual page 694

Bits 3    Clock Source Select Bit (CCS): Selects clock source of CTL.
Bit 3
CCS Description
φs
0
φs/2
1
Bit 2    Long CTL Bit (LCTL): Sets the long CTL detection mode.
Bit 2
LCTL Description
0 Clock source (CCS) operates at the setting value
1 Clock source (CCS) operates for further 8-division after operating at the setting
value
Bit 1    CTL Undetected Bit (UNCTL): Indicates the CTL pulse detection status at the CTL
input amplifier sensitivity set at the CTL gain control register.
Bit 1
UNCTL Description
0 Detected
1 Undetected
Bit 0    Mode Select Bit (SLWM): Selects CTL mode.
Bit 0
SLWM Description
0 Normal mode
1 Slow mode
Rev. 1.0, 02/00, page 688 of 1141
(Initial value)
(Initial value)
(Initial value)
(Initial value)