Enabling; Bcc Instruction - Hitachi H8S/2199 Hardware Manual

25.3.2

Enabling

The address trap function becomes valid after executing one instruction following the setting of
the enable bit of the address trap control register (TRCR) to 1.
029C
*029E
02A0
02A2
02A4
02A6
Note: * Trap setting address
25.3.3

Bcc Instruction

1. When the condition is satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is satisfied by
the Bcc instruction and then branched, transition is made to the address trap interrupt after
executing the instruction at the branch. The address to be stacked is 02A8.
φ
Address bus
Interrupt
request
signal
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Figure 25.6 When the Condition Satisfied by Bcc Instruction (8-bit Displacement)
BSET #0, @TRCR
MOV.W R0, R1
MOV.B R1L, R3H
NOP
CMP.W R0, R1
NOP
Figure 25.5 Enabling
BEQ NOP CMP
instruc- instruc- instruc-
tion tion tion
pre-fetch pre-fetch pre-fetch
029C 029E 02A6
BEQ
execu-
tion
After executing the MOV instruction,
the address trap interrupt does not
arise, and the next instruction is
executed.
NOP Start of
instruc-
exception
tion
handling
pre-fetch
02A8 02AA
CMP
execu-
tion
(NEXT = H'02A6)
029C BEQ NEXT:8
029E NOP
*
02A0 NOP
02A2 NOP
02A4 NOP
02A6 CMP.W R0, R1
02A8 NOP
Rev. 1.0, 02/00, page 537 of 1141