Hitachi H8S/2199 Hardware Manual page 745

Single-chip microcomputer
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H Complement Start Time Setting Register (HRTR)
Bit :
HRTR7
Initial value :
R/W :
HRTR is an 8-bit write-only register that sets the timing to generate a complementary pulse if a
pulse of the horizontal sync signal is missing.
If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, or in
stand-by or module stop mode.
((Value of HRTR7-0) + 1) × 2/φs = TH
where, TH is the period of the horizontal sync signal (µs), and φs is the servo clock (fosc/2).
Whether the horizontal sync signal exists or not is determined one clock before the
complementary pulse is generated. Accordingly, set to HRTR7 to HRTR0 a value obtained from
the equation shown above plus one.
Also, HRTR7-HRTR0 sets the noise mask period. If the horizontal sync signal has the normal
pulses, it is masked in the mask period.
The start and the end of the mask period are computed frm the rising edge of OSCH and SEPH,
respectively. See figure 26.75.
Complementary H Pulse Width Setting Register (HPWR)
Bit :
Initial value :
R/W :
HRWR is an 8-bit write-only register that sets the pulse width of the complementary pulse which
is generated if a pulse of the horizontal sync signal is missing. Bits 7 to 4 are reserved.
If a read is attempted, an undetermined value is read out. It is initialized to H'F0 by a reset or in
stand-by mode.
((Value of HPWR3-0) + 1) × 2/φs = Hpulse
Where, Hpuls is the pulse width of the horizontal sync signal (µs), and φs is the servo clock
(fosc/2).
7
6
HRTR6
HRTR5
0
0
W
W
7
6
1
1
5
4
HRTR4
HRTR3
0
0
W
W
5
4
HPWR3
1
1
3
2
HRTR2
HRTR1
0
0
W
W
3
2
HPWR2
HPWR1
0
0
W
W
Rev. 1.0, 02/00, page 739 of 1141
1
0
HRTR0
0
0
W
W
1
0
HPWR0
0
0
W
W

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