Hitachi H8S/2199 Hardware Manual page 1049

H'D119: Timer R Mode Register 2 TMRM2: Timer R
7
Bit :
LAT
0
Initial value :
R/W
R/W :
TMRU-2 captrue signal select bits
Note: * Don't care.
Note: * The CAPF bit and the SLW bit, respectively, works to latch the interrupt causes and writing 0
6 5
PS11 PS10
0 0
R/W R/W
Capture signal flag
Interrupt select bit
0 Interrupt request by TMRU-2 capture signal is enabled
1 Interrupt request by slow tracking mono-multi end is enabled
TMRU-3 clock source select bits
PS31 PS30
0 0
1
1 0
1
TMRU-1 clock source select bits
PS11 PS10
0 0 Count at CFG rising edge
PSS, count at φ/4
1
PSS, count at φ/256
1 0
PSS, count at φ/512
1
LAT CPS
0 * Capture at TMRU-3 underflow
1 0 Capture at CFG rising edge
1 Capture at IRQ3 edge
only is valid. Consequently, when these bits are being set to 1, respective interrupt requests
will not be issued. Therefore, it is necessary to check these bits during the course of the
interrupt processing routine to have them cleared.
Also priority is given to the set and, when an interrupt cause occur while the a clearing
command (BCLR, MOV, etc.) is being executed, the CAPF bit and the SLW bit will not be
cleared respectively and it thus becomes necessary to pay attention to the clearing timing.
4 3
PS31 PS30 CP/SLM
0 0
R/W R/W R/W
Slow tracking mono-multi flag
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When slow tracking mono-multi ends while
CP/SLM bit = 1
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When TMRU-2 capture signal is generated while CP/SLM bit = 0
Description
Count at rising edge of DVCTL from frequency divider
PSS, count at φ/4096
PSS, count at φ/2048
PSS, count at φ/1024
Description
(Initial value)
Description
(Initial value)
2 1 0
CAPF SLW
0 0 0
R/(W)* R/(W)*
(Initial value)
(Initial value)
Rev. 1.0, 02/00, page 1047 of 1141
(Initial value)
(Initial value)