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Bits 1 and 0 CFG Mask Timer Clock Selection Bits (CPS1, CPS0): Selects the clock source
for the CFG mask timer. (φs = fosc/2)
Bit 1
Bit 0
CPS1
CPS0
0
0
1
1
0
1
CFG Frequency Division Register 1 (CDIVR1)
Bit :
Initial value :
R/W :
CDIVR1 is an 8-bit write-only register to set the division value. If a read is attempted, an
undetermined value is read out. Bit 7 is reserved.
The frequency division value is written in the reload register and the down counter at the same
time.
CFG's frequency is divided by N at its rising edge or both edges If the register value is 0, no
division operation is performed, and the DVCFG signal with the same input cycle with CFG
signal is output. The DVCFG signal is sent to the capstan speed error detector. It is initialized to
H'80 by a reset or in stand-by mode together with the capstan frequency division register and the
down counter.
Description
φs/1024
φs/512
φs/256
φs/128
7
6
CDV16
CDV15
—
1
0
—
W
5
4
CDV14
CDV13
0
0
W
W
3
2
CDV12
CDV11
0
0
W
W
Rev. 1.0, 02/00, page 725 of 1141
(Initial value)
1
0
CDV10
0
0
W
W
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