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Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
No
IRIC=1?
Read ACKB bit in ICSR
No
End of transmission
(ACKB=1)?
Set TRS=0 in ICCR
Read ICDR
Clear IRIC flag in ICCR
End
Figure 23.17 Flowchart for Slave Receive Mode (Example)
23.3.10 Initializing Internal Status
The IIC can forcibly initialize the IIC internal status when a dead lock occurs during
communication. Initialization is enabled by (1) setting the CLR3 to CLR0 bits in DDCSWR, or (2)
clearing the ICE bit. For details on CLR3 to CLR0 settings, refer to section 23.2.8, DDC Switch
Register (DDCSWR).
(1) Initialized Status
This function initializes the following:
•
TDRE and RDRF internal flags
•
Transmit/receive sequencer and internal clock counter
•
Internal latches (wait, clock, or data output) which holds the levels output from the SCL and
SDA pins
This function does not initialize the following:
• Register contents (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR)
[1]
[2]
Yes
[3]
Yes
[4]
[5]
Set transmit data for the second and
[1]
subsequent bytes.
Wait for 1 byte to be transmitted.
[2]
[3]
Test for end of transfer.
Select slave receive mode.
[4]
Dummy read (to release the SCL line).
[5]
Rev. 1.0, 02/00, page 507 of 1141
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