Hitachi H8S/2199 Hardware Manual page 768

Bit 5    Csync Separation Comparator Input Select (CCMPSL): Controls internal switch SW5
to select whether to use the Csync separation comparator input or Csync Schmitt input. Writing 0
to this bit selects the Csync separation comparator input, and writing 1 selects the Csync Schmitt
input. This bit also controls the input/output status of the Csync/Hsync terminal. Writing 0 to this
bit makes the Csync/Hsync an output terminal, and writing 1 makes it an input terminal. Note that
the Csync/Hsync terminal enters a high-impedance state at reset and in sleep, subactive, subsleep,
watch, standby, and module stop modes.
Bit 5
CCMPSL Description
0 The Csync separation comparator input is selected
The Csync/Hsync terminal operates as an output terminal
1 The Csync Schmitt input is selected
The Csync/Hsync terminal operates as an input terminal
Bit 4    Sync Signal Polarity Select (SYNCT): This bit selects the polarity of the Csync/Hsync
and VLPF/Vsync input signals. When using the CVin2 input signal, be sure to write 0 to this bit to
select the positive polarity.
Bit 4
SYNCT Description
0
1
Bit 3    Vsync Input Signal Select (VSEL): Controls internal switch SW6 to select the Vsync
input signal. Writing 0 to this bit selects the Vsync Schmitt input, and writing 0 selects the Csync
Schmitt input.
Bit 3
VSEL Description
0 Vsync Schmitt input
1 Csync Schmitt input
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(Initial value)
(Initial value)
(Initial value)