Hitachi H8S/2199 Hardware Manual page 955

Single-chip microcomputer
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Instruction Mnemonic
DEC
DEC.B Rd
DEC.W #1/2,Rd
DEC.L #1/2 ERd
DIVXS
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
DIVXU
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
EEPMOV
EEPMOV.B
EEPMOV.W
EXTS
EXTS.W Rd
EXTS.L ERd
EXTU
EXTU.W Rd
EXTU.L ERd
INC
INC.B Rd
INC.W #1/2,Rd
INC.L #1/2,ERd
JMP
JMP @ERN
JMP @aa:24
JMP @@aa:8
JSR
JSR @ERn
JSR @aa:24
JSR @@aa:8
LDC
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
LDM
LDM.L
@SP+,(ERn−ERn+1)
LDM.L
@SP+,(ERn−ERn+2)
LDM.L
@SP+,(ERn−ERn+3)
LDMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
MAC
MAC @ERn+,@ERm+
Branch
Instruction
Address
Fetch
Read
I
J
1
1
1
2
2
1
1
2
2
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
2
1
1
2
2
3
3
5
5
2
2
3
3
4
4
2
2
2
Cannot be used in this LSI.
Stack
Byte Data
Operation
Access
K
L
*2
2n+2
*2
2n+2
2
2
2
4
6
8
Rev. 1.0, 02/00, page 953 of 1141
Word Data
Internal
Access
Operation
M
N
11
19
11
19
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

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