Hitachi H8S/2199 Hardware Manual page 1090

Single-chip microcomputer
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H'D249: Data Slicer Detection Window Register DDETWR: Sync Separator
7
:
Bit
SRWDE1
Initial value
:
0
R/W
:
W
Start bit detection window signal falling timing setting
SRWDE1 SRWDE0
Rev. 1.0, 02/00, page 1088 of 1141
6
5
SRWDE0
SRWDS1
SRWDS0
0
0
W
W
Clock run-in detection window signal rising timing setting
CRWDS1 CRWDS0
0
1
Clock run-in detection window signal falling timing setting
CRWDE1 CRWDE0
0
0
1
1
0
1
Start bit detection window signal rising timing setting
SRWDS1 SRWDS0
The detection starts about 23.5 µs after the slicer start point (Initial value)
0
0
The detection starts about 23.0 µs after the slicer start point
1
The detection starts about 24.0 µs after the slicer start point
1
0
This setting must not be used
1
The detection ends about 29.5 µs after the slicer start point (Initial value)
0
0
The detection ends about 29.0 µs after the slicer start point
1
The detection ends about 30.0 µs after the slicer start point
1
0
This setting must not be used
1
4
3
CRWDE1
CRWDE0 CRWDS1 CRWDS0
0
0
W
W
The detection starts about 10.5 µs after the slicer start point (Initial value)
0
The detection starts about 10.0 µs after the slicer start point
1
The detection starts about 11.0 µs after the slicer start point
0
This setting must not be used
1
Description
The detection ends about 23.5 µs after the slicer start point (Initial value)
The detection ends about 23.0 µs after the slicer start point
The detection ends about 24.0 µs after the slicer start point
This setting must not be used
Description
Description
2
1
0
0
0
0
W
W
W
Description

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