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H'D02A: Digital Filter Control Register DFUCR: Digital Filter
Bit :
7
—
Initial value :
1
—
R/W :
Rev. 1.0, 02/00, page 992 of 1141
6
5
4
—
PTON
CP/DP
1
0
0
—
R/W
R/W
Capstan phase system error data transfer bit
0 Transfer data by DVCFG2 signal latch. (Initial value)
1 Transfer data at the time of error data write.
PWM output select bit
0 Output drum phase system computation result (CAPPWM) (Initial value)
1 Output capstan phase system computation result (DRMPWM)
Phase system computation result PWM output bit
0 Output normal filter computation result to PWM pin. (Initial value)
1 Output only phase system computation result to PWM pin.
3
2
1
CFEPS
DFEPS
CFESS
0
0
0
R/W
R/W
R/W
Capstan speed system error data transfer bit
0 Transfer data by DVCFG signal latch. (Initial value)
1 Transfer data at the time of error data write.
Drum phase system error data transfer bit
0 Transfer data by HSW (NHSW) signal latch. (Initial value)
1 Transfer data at the time of error data write.
0
DFESS
0
R/W
Drum speed system error data transfer bit
0 Transfer data by NCDFG signal latch. (Initial value)
1 Transfer data at the time of error data
write.
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