Pin Configuration; Register Configuration; Timer Mode Register J (Tmj) - Hitachi H8S/2199 Hardware Manual

13.1.3

Pin Configuration

Table 13.1 shows the pin configuration of timer J.
Table 13.1 Pin Configuration
Name
Event input pin
Event input pin
13.1.4

Register Configuration

Table 13.2 shows the register configuration of timer J.
The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively.
Reading or writing determines the accessing register.
Table 13.2 Register Configuration
Name
Timer mode register J
Timer J control register
Timer J status register
Timer counter J
Timer counter K
Timer load register J
Timer load register K
Notes: 1. Only 0 can be written to clear the flag.
2. Lower 16 bits of the address.
Abbrev. I/O
,544
Input
,545
Input
Abbrev. R/W
TMJ R/W
TMJC R/W
TMJS R/(W)
TCJ R
TCK R
TLJ W
TLK W
Function
Event inputs to the TMJ-1
Event inputs to the TMJ-2
Size
Byte
Byte
*1
Byte
Byte
Byte
Byte
Byte
Rev. 1.0, 02/00, page 263 of 1141
Initial Value Address
H'00 H'D13A
H'09 H'D13B
H'3F H'D13C
H'FF H'D139
H'FF H'D138
H'FF H'D139
H'FF H'D138
*2