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H'D220: Slice Even-Field Mode Register SEVFD: Data Slicer
15
:
Bit
EVNIE
:
Initial value
:
R/W
R/W
Even field slice completion interrupt enable flag
Disables even-field slice completion interrupt
0
Enables even-field slice completion interrupt
1
:
Bit
SLVLE2
Initial value
:
R/W
:
R/W
Slice Level Setting Bits
SLVLE2 SLVLE1 SLVLE0
0
1
Note: All slice levels are with reference to the pedestal level (5 IRE).
Slice level values are provided for reference.
Note: * Only 0 can be written to clear the flag.
14
13
EVNIF
0
0
R/(W)*
Even field slice interrupt completion flag
0
[Clearing condition]
When 0 is written after reading 1
1
[Setting condition]
When data slicing is completed for all specified lines of even field
7
6
SLVLE1
SLVLE0
0
0
R/W
R/W
0
0
Slice level is 0 IRE
1
Slice level is 5 IRE
1
0
Slice level is 15 IRE
1
Slice level is 20 IRE
0
0
Slice level is 25 IRE
1
Slice level is 35 IRE
1
0
Slice level is 40 IRE
1
Must not be specified
12
STBE4
STBE3
—
1
0
R/W
R/W
—
Start bit detection starting position bits
(Initial value)
5
4
DLYE4
DLYE3
0
0
R/W
R/W
Description
(Initial value)
11
10
STBE2
STBE1
0
0
R/W
R/W
(Initial value)
3
2
DLYE2
DLYE1
0
0
R/W
R/W
Even field data sampling clock delay time
Rev. 1.0, 02/00, page 1079 of 1141
9
8
STBE0
0
0
R/W
1
0
DLYE0
0
0
R/W
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