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Section 27 Sync Separator for OSD and Data Slicer
27.1
Overview
The sync separator separates the horizontal sync signal and vertical sync signal from the
composite video signal input from the CVin2 terminal and sends the sync signals to the on screen
display (OSD) module and data slicer.
The sync separator has an automatic frequency controller (AFC), which generates a reference
clock at 576 or 448 times the horizontal sync signal frequency. This reference clock is used to
separate the horizontal sync signal from the composite video signal. The AFC receives the Hsync
signal processed by the H complement and mask counter. The H complement and mask counter
removes noise and equalizing pulses from the Hsync signal and interpolates necessary pulses for
the Hsync signal.
The sync separator separates the vertical sync signal from the composite video signal through the
counting operation of the V complement and mask counter. The V complement and mask counter
increments the count at double the frequency of the horizontal sync signal to mask the Vsync
noise and to generate complementary pulses for the Vsync signal according to the register settings.
Through the above functions, the sync signals can be separated correctly against noise input to the
CVin2 terminal, motor skew due to VCR tape playback or special-function playback, and
abnormal noise in a weak field.
In addition, the sync separator provides the field detection function necessary for the data slicer,
and the noise detection function necessary for tuner detection (detecting the tuning status).
As the AFC reference clock is also used as the dot clock of the OSD, switching the reference clock
can change the dot width of the display. When the text display mode of the OSD is used, refer to
section 27.3.6, Automatic Frequency Controller (AFC).
In addition to the CVin2 video signal, the following signals can be selected as sources of sync
separation through the external circuit and register settings: the Csync composite sync signal input
from the Csync/Hsync terminal, and the separate Vsync and Hsync signals input from the
VLPF/Vsync and Csync/Hsync terminals, respectively.
Rev. 1.0, 02/00, page 757 of 1141
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