Noise Canceler; Sample Flowcharts - Hitachi H8S/2199 Hardware Manual

23.3.8

Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 23.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
SCL or SDA
input signal
Sampling
clock
23.3.9

Sample Flowcharts

Figures 23.14 to 23.17 show sample flowcharts for using the I
Sampling clock
C
D Q
Latch
System clock
period
Figure 23.13 Block Diagram of Noise Canceler
C
D Q
Latch
2
C bus interface in each mode.
Match
detector
Rev. 1.0, 02/00, page 503 of 1141
Internal SCL
or SDA signal