Table of Contents
Advertisement
H'D058: Capstan Speed Error Detection Control Register
Bit :
7
CFCS1
0
Initial value :
R/W
R/W :
Clock source select bit
CFCS1 CFCS0
0
0
1
1
0
1
Notes:
1. Only 0 can be written.
2. When read, counter value is read.
Rev. 1.0, 02/00, page 998 of 1141
6
5
4
CFCS0
CFOVF
CFRFON CF-R/UNR CPCNT
0
0
0
*1
R/W
R/(W)
R/W
Error data limit function select bit
0
Limit function OFF (Initial value)
1
Limit function ON
Counter overflow flag
0
Normal status (Initial value)
1
Counter overflows.
Description
φs (Initial value)
φs/2
φs/4
φs/8
CFVCR: Capstan Speed Error Detector
3
2
0
0
R
R/W
Capstan lock counter setting bit
CFRCS1 CFRCS0
0
1
Capstan phase system filter computation auto start bit
0
Filter computation by capstan lock detection is not excuted. (Initial value)
1
Filter computation of phase system is executed at the time of
drum lock detection.
Capstan lock flag
0
Capstan speed system is not locked. (Initial value)
1
Capstan speed system is locked.
1
0
CFRCS1
CFRCS0
0
0
*2
*2
(R)/W
(R)/W
Description
0
Underflow by 1 lock detection (Initial value)
1
Underflow by 2 lock detections
0
Underflow by 3 lock detections
1
Underflow by 4 lock detections
Advertisement
Table of Contents
