Hitachi H8S/2199 Hardware Manual page 447

Single-chip microcomputer
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Figure 22.12 shows an example of SCI operation for transmission using a multiprocessor format.
Start
1
bit
0
D0
TDRE
TEND
Data written to TDR1 and
TXI interrupt
TDRE flag cleared to 0
request
in TXI interrupt handling
general
routine
Figure 22.12 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
b. Multiprocessor Serial Data Reception
Figure 22.13 shows sample flowcharts for multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
Rev. 1.0, 02/00, page 438 of 1141
Multi-
Data
processor
bit
D1
D7
0/1
TXI interrupt request
generated
1 frame
Stop
Start
bit
bit
1
0
D0
D1
Multi-
Data
processor
Stop
bit
bit 1
D7
0/1
1
TEI interrupt
request
generated
Idle state
(mark state)

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