Hitachi H8S/2199 Hardware Manual page 602

Bit 4    DFG Edge Selection Bit (EDG): Selects the edge by which to count DFG pulses.
Bit 4
EDG Description
0 Counts by the rising edge of DFG
1 Counts by the falling edge of DFG
Bit 3    Interrupt Selection Bit (ISEL1): Selects the interrupt source. (IRRHSW1)
Bit 3
ISEL1 Description
0 Generates an interrupt request by the rising edge of the STRIG signal of FIFO
1 Generates an interrupt request by the matching signal of FIFO
Bit 2    FIFO Output Group Selection Bit (SOFG): Selects whether 20 stages of FIFO1 +
FIFO2 or only 10 stages of FIFO1 are used.
If 20-stage output mode is used in single mode, data must be written to FIFO1 and FIFO2.
Monitor the output FIFO group flag (OFG) and control data writing by software. All the data of
FIFO1 is output, then all the data of FIFO2 is output. These steps are repeated. If 10-stage output
mode is used, the data of FIFO2 is not reflected.
Modifying the SOFG bit from 0 to 1, then again to 0 initializes the control signal of the FIFO
output stage to the FIFO1 side.
Bit 2
SOFG Description
0 20-stage output of FIFO1 + FIFO2
1 10-stage output of FIFO1 only
Bit 1    Output FIFO Group Flag (OFG): Indicates the FIFO group which is outputting.
Bit 1
OFG Description
0 Pattern is being output by FIFO1
1 Pattern is being output by FIFO2
Rev. 1.0, 02/00, page 596 of 1141
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