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H'D039: Drum Phase Error Detection Control Register
Bit :
DPCS1
Initial value :
R/W
R/W :
Clock source select bit
DPCS1 DPCS0
0
1
Note: * Only 0 can be written.
7
6
DPCS0
DPOVF
0
0
R/W
R/(W)*
Counter overflow flag
0
Normal status (Initial value)
1
Counter overflows.
Description
φs (Initial value)
0
φs/2
1
φs/4
0
φs/8
1
DPGCR: Drum Phase Error Detector
5
4
N/V
HSWES
0
0
R/W
R/W
Edge select bit
0
Latch at rising edge (Initial value)
1
Latch at falling edge
Error data latch signal select bit
0
HSW (VideoFF) signal (Initial value)
1
NHSW (NarrowFF) signal
3
2
—
0
1
—
Rev. 1.0, 02/00, page 995 of 1141
1
0
—
—
1
1
—
—
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