Hitachi H8S/2199 Hardware Manual page 283

Bit 1    Enabling Interrupt of the TMJ1I (TMJ1IE): This bit works to permit/prohibit
occurrence of TMJ1I interrupt of the TMJS in 1-set of the TMJ1I.
Bit 1
TMJ1IE Description
0 Prohibits occurrence of TMJ1I interrupt
1 Permits occurrence of TMJ1I interrupt
Bit 0    TMJ-2 Input Clock Selection (PS22): This bit, together with the PS21 and PS20 bits of
the timer mode register J (TMJ), selects the TMJ-2 input clock source.
TMJC
Bit 3 Bit 0 Bit 3
EXN PS22 PS21
0 1 0
1
0 *
1 1 0
1
0 0
1
Note: * Don't care
1. The external clock edge can be selected by the IRQ edge select register (IEGR). For
details, refer to section 6.2.4, IRQ Edge Select Registers (IEGR).
TMJ
Bit 2
PS20 Description
PSS; count at φ/128
0
PSS; count at φ/64
1
0 Count at TMJ-1 underflow
1 External clock (IRQ2); count at rising or falling edge*
* Reserved
PSS; count at φ/16384
0
PSS; count at φ/2048
1
0 Count at TMJ-1 underflow
1 External clock (IRQ2); count at rising or falling edge*
PSS; count at φ/1024
0
PSS; φ/1024
1
0 Count at TMJ-1 underflow
1 External clock (IRQ2); count at rising or falling edge*
(Initial value)
Rev. 1.0, 02/00, page 269 of 1141
(Initial value)
1
1
1