Interrupt Control Mode 0 - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Operations and Control Signal Functions in Each Interrupt Control Mode

Interrupt operation control performed

Used as interrupt mask bit

Sets priority

Interrupt Control Mode 0

Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by

the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and

disabled when set to 1. Control level 1 interrupt sources have higher priority.

Figure 6.5 shows a flowchart of the interrupt acceptance operation in this case.

• If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

• When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,

according to the control level set in ICR, has priority for selection, and other interrupt requests

are held pending. If a number of interrupt requests with the same control level setting are

generated at the same time, the interrupt request with the highest priority according to the

priority system shown in table 6.4 is selected.

• The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the

I bit is set to 1, only an NMI*

requests are held pending.

• When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

• The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the

interrupt handling routine.

• Next, the I bit in CCR is set to 1. This disables all interrupts except NMI* and address trap.

• A vector address is generated for the accepted interrupt, and execution of the interrupt

handling routine starts at the address indicated by the contents of that vector address.

Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.

Interrupt Acceptance Control,

3-Level Control

or an address trap interrupt is accepted, and other interrupt

Rev. 1.0, 02/00, page 113 of 1141

Default Priority

Determination