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26.14
Frequency Dividers
26.14.1 Overview
On-chip frequency dividers are provided for the pulse signal picked up from the control track
during playback (the PB-CTL signal), and the pulse signal received from the capstan motor (CFG
signal). The CTL frequency divider generates a CTL divided control signal (DVCTL) from the
PB-CTL signal, for use in capstan phase control during high-speed search, for example. The CFG
frequency divider generates two divided CFG signals (DVCFG for speed control and DVCFG2 for
phase control) from the CFG signal. The DFG noise canceller is a circuit which considers signal
less than 2φ as noise and mask it.
26.14.2 CTL Frequency Divider
Block Diagram: Figure 26.63 shows a block diagram of the CTL frequency divider.
CTVC
EXCTL
detector
PB-CTL↑
Register Description
− Register configuration
Table 26.22 shows the register configuration of the CTL frequency dividers.
Table 26.22
Register Configuration
Name
DVCTL control register
CTL frequency division
register
Rev. 1.0, 02/00, page 718 of 1141
Internal bus
R/W
R/W
CTVC
CEG
CEX
Edge
↑, ↓
Figure 26.63 CTL Frequency Divider
Abbrev.
CTVC
CTLR
W
CTL division register
Down counter (8 bits)
R/W
Size
R/W
Byte
W
Byte
CTLR
(8 bits)
UDF
Initial Value
Undefined
H'00
DVCTL
Address
H'D098
H'D099
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