Hitachi H8S/2199 Hardware Manual page 633

Single-chip microcomputer
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• Interrupt request
IRRDRM1 is generated by the NCDFG signal latch and the overflow of the error detection
counter. IRRDRM2 is generated by detection of lock (after the detection of the specified
number of times of locking).
NCDFG signal
Error data latch
signal (DFG ↑)
Preset data
load signal
Preset period
Specified speed value
(2 counts)
–value+value
Counter
Preset value
Latch data 0
(no error)
Figure 26.28 Example of the Drum Speed Error Detection
(When the Rising Edge of DFG is Selected)
Rev. 1.0, 02/00, page 627 of 1141

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