Hitachi H8S/2199 Hardware Manual page 1004

H'D061: HSW Mode Register 2 HSM2: HSW Timing Generator
Bit : 7
FRT
0
Initial value :
R/W
R/W :
FRG2 clear stop bit
0
1 16-bit timer counter clearing by DFG reference register 2 is disabled
Free-run bit
0 5-bit DFG counter and 16-bit timer counter
1 16-bit FRC
Rev. 1.0, 02/00, page 1002 of 1141
6 5
FGR20FF LOP EDG
0 0
R/W R/W R/W
DFG edge select bit
0 Calculated by DFG rising edge
1 Calculated by DFG falling edge
Mode select bit
0 Signal mode
1 Loop mode
16-bit timer counter clearing by DFG reference register 2 is enabled
4 3 2
ISEL1 SOFG
0 0 0
R/W R/W
Output FIFO group flag
FIFO output group select bit
0 20-stage output by FIFO1 and FIFO2
1 10-stage output by FIFO1 only
Interrupt select bit
0 Interrupt request is generated by rising of FIFO STRIG signal
1 Interrupt request is generated by FIFO match signal
(Initial value)
(Initial value)
1 0
OFG VFF/NFF
0 0
R R/W
VideoFF/NallowFF output switchover bit
0 VideoFF output
1 NarrowFF output
0 Outputting pattern by FIFO1 (Initial value)
1 Outputting pattern by FIFO2
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)