Hitachi H8S/2199 Hardware Manual page 543

2. Figure 25.3 shows the operation when the instruction immediately preceding the trap address
is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the
second state from the last. The address to be stacked is 0268.
φ
Address bus
Interrupt
request
signal
Note: * Trap setting address
The underlines address is the one to be actually stacked.
3. Figure 25.4 shows the operation when the instruction immediately preceding the trap address
is that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to be
stacked is 025C.
φ
Address bus
Interrupt
request
signal
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Rev. 1.0, 02/00, page 536 of 1141
Data
MOV NOP NOP
instruc- instruc- read instruc-
tion tion
pre-fetch pre-fetch pre-fetch
0266 0268 0000 026A
NOP
MOV
execution
execution
Figure 25.3 Basic Operations (2)
NOP NOP NOP
instruc- instruc- instruc-
tion tion tion
pre-fetch pre-fetch pre-fetch pre-fetch
0256 0258 025A
NOP NOP
execu- execu-
tion tion
Figure 25.4 Basic Operations (3)
Start of exception
handling
tion
026C
NOP Start of
instruc-
exception
tion
handling
025C 025E
NOP
execu-
tion
Immediately Address
→
preceding
0266
instruction
R2L, @0000
*
0268
026A
026C
Address
→
0256
Immediately
0258
preceding *
025A
instruction
025C
025E
MOV.B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP