Field Detection; Noise Detection - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Field Detection

The sync separator detects whether the current field is an even field or an odd field from the 1/2H

phase difference between the Hsync and Vsync by using the AFCV signal generated by the V

complement and mask counter and the field detection window signal generated by the AFC. The

timing of the field detection window signal can be adjusted by the FWIDR setting so that it is

suitable for comparison with the AFCV signal. When a rising edge of the AFCV signal is detected

while the field detection window signal is high, the current field is determined as an odd field;

when a rising edge of the AFCV signal is detected while the field detection window signal is low,

the current field is determined as an even field. The field detection status can be monitored from

the CPU by reading the FLD bit (bit 0) of the SEPACR. This function will not operate when the

internally generated Hsync signal is selected as the reference Hsync signal for the AFC, because

the AFC is not synchronized with the external Hsync signal in this case. For the timing, refer to

figure 27.11.

The noise detection function is necessary for tuned status detection. The sync separator detects

noise by using the Csync signal and the noise detection window signal generated by the H

complement and mask counter. The noise detection window signal is set to 1 at a falling edge of

the OSCH signal generated by the H complement and mask counter, and reset to 0 at the HHK

clearing timing specified by bits 6 to 0 of the HCMMR. Noise is detected by comparing the noise

counter value with the noise detection level register value. The noise counter counts the number of

Hsync cycles in which an Hsync signal is input (noise H) while the noise detection window signal

is high and the number of Hsync cycles in which no Hsync signal is input while the noise

detection window signal is low. When the counted value reaches the noise detection level, the

noise detection interrupt request flag is set. The noise counter can be read from the CPU, and the

noise detection status can be monitored. The noise detection counter is reset every other Vsync

signal input. Accordingly, the noise input during one field can be detected. When the internally

generated Hsync signal is selected as the reference Hsync signal for the AFC and the text display

mode is used in the OSD, the noise counter reset operation can be enabled by setting the VCKSL

bit (bit 5) of the SEPCR to 1. For the timing, refer to figure 27.13.

Rev. 1.0, 02/00, page 792 of 1141