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DFG Speed Error Data Register (DFER)
15
Bit :
DFER15
Initial value :
0
R/W :
R*/W
7
Bit :
DFER7
Initial value :
0
R/W :
R*/W
Note: Note that only detected error data can be read.
DFER is a 16-bit read/write register that stores 16-bit DFG speed error data. When the drum
motor speed is correct, the data latched in DFER is H'0000. Negative data will be latched if the
speed is faster than the specified speed, and positive data if the speed is slower than the specified
speed. The DFER value is sent to the digital filter either automatically or by software.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed.
DFER is initialized to H'0000 by a reset, and in standby mode and module stop mode.
Refer to the note Specified DFG Speed Preset Data Register (DFPR) in 26.6.4 Register
Description.
DFG Lock Upper Data Register (DFRUDR)
Bit :
15
DFRUDR15
Initial value :
R/W :
W
Bit :
DFRUDR7
Initial value :
R/W :
W
DFRUDR is a 16-bit write-only register used to set the lock range on the UPPER side when drum
speed lock is detected, and to set the limit value on the UPPER side when limiter function is in
use. Set a signed data to DFRUDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
which has been set by DFRCS 1 and 0 bits of DFVCR register decrements the count. If the set
value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation
of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG
speed error data exceeds the DFRUDR value within the limiter function is in use, the DFRUDR
value can be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF
by a reset, or in stand-by or module-stop mode.
Rev. 1.0, 02/00, page 622 of 1141
14
13
DFER14
DFER13
0
R*/W
R*/W
6
DFER6
DFER5
0
R*/W
R*/W
14
13
DFRUDR14 DFRUDR13
0
1
W
W
7
6
DFRUDR6 DFRUDR5
1
1
W
12
DFER12
DFER11
0
0
R*/W
R*/W
5
4
DFER4
DFER3
0
0
R*/W
R*/W
12
DFRUDR12 DFRUDR11 DFRUDR10 DFRUDR9 DFRUDR8
1
1
W
5
4
DFRUDR4 DFRUDR3 DFRUDR2 DFRUDR1 DFRUDR0
1
1
W
W
11
10
DFER10
DFER9
0
0
R*/W
R*/W
3
2
DFER2
DFER1
0
0
R*/W
R*/W
11
10
1
1
W
W
3
2
1
1
W
W
9
8
DFER8
0
0
R*/W
1
0
DFER0
0
0
R*/W
9
8
1
1
W
W
1
0
1
1
W
W
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