Hitachi H8S/2199 Hardware Manual page 718

Detection of the Long/Short Pulse: The long/short pulse is detected in PB mode by the L/S
determination based on the comparison of the REC-CTL duty register (RCDR2 to RCDR5) with
the up/down counter and the results of the duty I/O flag. The results of the determination is stored
in bit 0 (LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting at the
same time BTPR leftward.
RCDR2-5 set the L/S thresholds for each of FWD/REV. Set to RCDR2 a threshold of 1 pulse L/S
for FWD, to RCDR3 a threshold of 0 pulse L/S for FWD, to RCDR4 a threshold of 0 pulse L/S for
REV, and to RCDR5 a threshold of 1 pulse L/S for REV. Figure 26.59 shows the detection of
long/short pulse.
Also, the bit pattern of 8-bit can be detected by BTPR. Check that an 8-bit detection has been
done by bit 1 (BPF bit) of the duty I/O register, and then read BTPR.
RCDR2 (12bit)
RCDR3 (12bit)
RCDR4 (12bit)
RCDR5 (12bit)
φs/4
Rev. 1.0, 02/00, page 712 of 1141
High-order 12-bit data
Up/Down counter (16-bit)
Figure 26.59 Detection of Long/Short Pulse
Internal bus
BTPR
Bit patter register (8 bits)
S Q
R
S Q
FW/RV
R
Note: L/S is determined at the rising edge of PB-CTL.
After the determination, bit pattern register is
shifted leftward, and the results of the determination
is stored in the LSB.
R
Shift left-ward
LSB
DI/O