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2
H'D0E8: I
C Bus Control Register ICCR0: I
Bit :
7
6
ICE
IEIC
Initial value :
0
0
R/W :
R/W
R/W
I
C bus interface interrupt enable
2
0 Interrupt request is disab led
1 Interrupt request is enabled
I
2
C bus interface enable
2
0 I
C bus interface module disabled, with SCL and SDA signal pins
set to port function. SAR and SARX can be accessed.
2
1 I
C bus interface module enabled for transfer operation (pins SCL
and SCA are driving the bus). ICMR and ICDR can be accessed.
Note: * Only 0 can be written to clear the flag.
Rev. 1.0, 02/00, page 1032 of 1141
5
4
3
MST
TRS
ACKE
0
0
0
R/W
R/W
R/W
Bus busy
0 Bus is free
1 Bus is busy
Acknowledge bit judgment selection
0 The value of the acknowledge bit is ignored, and continuous transfer is performed
1 If the acknowledge bit is 1, continuous transfer is interrupted
Master/slave select
Transmit/receive select
MST
TRS
Description
0
0
Slave receive mode
1
Slave transmit mode
1
0
Master receive mode
1
Master transmit mode
(Initial value)
2
C Bus Interface
2
1
0
BBSY
IRIC
SCP
0
0
1
R/W
R/(W)*
W
Start condition/stop condition prohibit
0 Writing 0 issues a start or stop condition, in combination
with the BBSY flag
1 Reading always returns a value of 1
Writing is ignored
I
2
C bus interface interrupt request flag
0
Waiting for transfer, or transfer in progress
[Clearing conditions]
(1) When 0 is written in IRIC after reading IRIC = 1
1
Interrupt requested
[Setting conditions]
2
• I
C bus format master mode
— When a start condition is detected in the bus line state after a start condition is
issued (when the TDRE flag is set to 1 because of first frame transmission)
— When a wait is inserted between the data and acknowledge bit when WAIT = 1
— At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
— When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
— When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
2
• I
C bus format slave mode
— When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1) and at the end of data transfer up
to the subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
— When the general call address is detected
(when the ADZ flag is set to 1) and at the end of data transfer up to the
subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
— When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
— When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
• Synchronous serial format
— At the end of data transfer (when the TDRE or RDRF flag is set to 1)
— When a start condition is detected with serial format selected
— When a condition, other than the above, that sets the TDRE or RDRF flag to 1 is
detected
[Clearing conditions]
When a stop condition is detected
[Setting conditions]
When a start condition is detected
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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