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Bit 0 Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting,
and in synchronous mode.
Bit 0
MPBT
Description
0
Data with a 0 multiprocessor bit is transmitted
1
Data with a 1 multiprocessor bit is transmitted
22.2.8
Bit Rate Register 1 (BRR1)
Bit :
Initial value :
R/W :
BRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR1 can be read or written to by the CPU at all times.
BRR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Table 22.3 shows sample BRR1 settings in asynchronous mode, and table 22.4 shows sample
BRR1 settings in synchronous mode.
7
6
1
1
R/W
R/W
5
4
1
1
R/W
R/W
3
2
1
1
R/W
R/W
Rev. 1.0, 02/00, page 413 of 1141
(Initial value)
1
0
1
1
R/W
R/W
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