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H'D07C: Capstan 12-Bit PWM Data Register CPWDR: Capstan 12-Bit PWM
Bit
:
15
14
—
—
Initial value
:
1
1
—
—
R/W
:
H'D080: CTL Control Register CTCR: CTL Circuit
Bit
:
7
NT/PL
Initial value
:
R/W
:
0
W
Operating frequency select bits
FSLC
Note: * Don't care.
NTSC/PAL select bit
0 NTSC mode (frame rate: 30 Hz)
1 PAL mode (frame rate: 25 Hz)
Rev. 1.0, 02/00, page 1014 of 1141
13
12
11
10
—
—
CPWDR11
CPWDR10
1
1
0
—
—
R/W
R/W
6
5
FSLC
FSLB
0
1
W
W
Clock source select bit
0 φs
1 φs/2
FSLB
FSLA
0
0
0
Reserved (do not set)
1
Reserved (do not set)
1
0
fosc = 8 MHz
1
fosc = 10 MHz
1
*
*
Reserved (do not set)
9
8
7
CPWDR9
CPWDR8
CPWDR7
CPWDR6
0
0
0
0
R/W
R/W
R/W
4
3
FSLA
CCS
LCTL
1
0
W
W
W
Long CTL bit
0 Clock source (CCS) operates at the setting value
1 Clock source (CCS) operates for further 8-division after
operating at the setting value
(Initial value)
Description
(Initial value)
(Initial value)
6
5
4
3
CPWDR5
CPWDR4
CPWDR3
0
0
0
0
R/W
R/W
R/W
R/W
2
1
0
UNCTL
SLWM
0
0
0
R
W
Mode select bit
0 Normal mode (Initial value)
1 Slow mode
CTL undetected bit
0 Detected
(Initial value)
1 Undetected
2
1
0
CPWDR2
CPWDR1
CPWDR0
0
0
0
R/W
R/W
R/W
(Initial value)
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