Hitachi H8S/2199 Hardware Manual page 783

Single-chip microcomputer

Table of Contents

Digital H separation

H complement and

mask counter

(for counter reset)

(for OSCH generation)

Figure 27.12 Complement and Mask Timing of the H Complement and Mask Counter

Bits 15 to 7    H Complementary Pulse Setting (HC8 to HC0): Specify the timing for

generating a complementary pulse when an Hsync pulse is lost. If no Hsync pulse is input within

the specified time, a complementary pulse is generated from the H complement and mask counter

and interpolated to the OSCH signal.

The following shows examples of HC8 to HC0 settings.

(HC + 1) × (2/OSC) > 63.5 µs (PAL: 64

System clock OSC = 10 MHz

2/OSC: 5 MHz (0.2 µs

Example 1: To set the timing for NTSC

HC8 to HC0 value = H'13E (318)

Example 2: To set the timing for PAL

HC8 to HC0 value = H'141 (321)

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