Competing Interrupt - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

5. SLEEP Instruction 5 (Standby or Watch Mode Setting)

When the trap address is the next instruction to the SLEEP instruction, this puts in the standby

(watch) mode after execution of the SLEEP instruction. After that, if the standby (watch)

mode is cancelled by the NMI interruption, transition is made to the NMI interrupt following

the CCR and PC (at the address of 0266) stack saving and vector reading. However, if the

address trap interrupt arises before starting execution of the NMI interrupt processing,

transition is made to the address trap exception handling. The address to be stacked is the

starting address of the NMI interrupt processing.

Note: * Trap setting address

Figure 25.20 SLEEP Instruction (5) (Standby or Watch Mode Setting)

Competing Interrupt

1. General Interrupt (Interrupt other than NMI)

When the ATC interrupt request is made at the timing in (1) (A) against the general interrupt

request, the interruption appears to take place in the ATC at the timing earlier than usual,

because higher priority is assigned to the ATC interrupt processing (Simultaneous interrupt

with the general interrupt has no effect on processing). The address to be stacked is 029E.

For comparison, the case where the trap address is set at 02A0 if no general interrupt request

was made is shown in (2). The address to be stacked is 02A4.

Rev. 1.0, 02/00, page 550 of 1141

interruption

Address trap