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H'D0B8: Servo Interrupt Enable Register 1 SIENR1: Servo Interrupt
7
Bit
:
IEDRM3
0
Initial value :
:
R/W
:
R/W
Drum speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM2 (Initial value)
1 Interrupt request is enabled by IRRDRM2
Drum phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRDRM3
1 Interrupt request is enabled by IRRDRM3
6
5
4
IEDRM2
IEDRM1
IECAP3
0
0
0
R/W
R/W
R/W
Capstan phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRCAP3 (Initial value)
1 Interrupt request is enabled by IRRCAP3
Drum speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM1 (Initial value)
1 Interrupt request is enabled by IRRDRM1
(Initial value)
3
2
IECAP2
IECAP1
0
0
R/W
R/W
HSW timing generation (counter clear, capture)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW2 (Initial value)
1 Interrupt request is enabled by IRRHSW2
Capstan speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP1 (Initial value)
1 Interrupt request is enabled by IRRCAP1
Capstan speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP2 (Initial value)
1 Interrupt request is enabled by IRRCAP2
1
0
IEHSW2
IEHSW1
0
0
R/W
R/W
HSW timing generator (OVW, match, STRIG)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW1
1 Interrupt request is enabled by IRRHSW1
Rev. 1.0, 02/00, page 1027 of 1141
(Initial value)
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