Hitachi H8S/2199 Hardware Manual page 500

Start condition
issuance
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TDRE
IRIC
ICDRT
ICDRS
User processing
[2] Write BBSY=1 and
SCP=0 (Start
condition issuance)
Figure 23.6 Example of Timing in Master Transmit Mode (MLS = WAIT = 0)
Rev. 1.0, 02/00, page 492 of 1141
1 2 3
Bit 7 Bit 6 Bit 5
Slave address
Interrupt
request
generated
Address + RW
Address + RW
[3] Write ICDR
4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1
[3] Clear IRIC
8 9 1
Bit 0 Bit 7
[4]
R/W
A
Interrupt request
generated
Data 1
Data 1
[5] Write ICDR [5]
2
Bit 6
Data 1
Clear IRIC