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Master transmit
mode
SCL
(Master output)
9
SDA
A
(Slave output)
SDA
(Master output)
RDRF
Interrupt
IRIC
request
generated
ICDRS
ICDRR
Clear
User
IRIC
processing
Figure 23.8 Example of Timing in Master Receive Mode (MLS = WAIT = ACKB = 0)
Master receive
mode
1
2
3
Bit 7
Bit 6
Bit 5
[1]Clear TRS to 0
[2]Read ICDR
(dummy read)
4
5
6
7
Bit 4
Bit 3
Bit 2
Bit 1
Data 1
[4] Read ICDR
Rev. 1.0, 02/00, page 495 of 1141
8
9
1
2
Bit 0
Bit 7
Bit 6
Data 2
[3]
A
Interrupt
request
generated
Data 2
Data 1
[4] Clear IRIC
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